109 lines
4.3 KiB
Markdown
109 lines
4.3 KiB
Markdown
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# Supermicro X9SAE and X9SAE-V
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This page describes how to run coreboot on the Supermicro [X9SAE] and [X9SAE-V]
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## Flashing coreboot
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```eval_rst
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+---------------------+----------------+
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| Type | Value |
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+=====================+================+
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| Socketed flash | occasionally |
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+---------------------+----------------+
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| Model | W25Q128FVSG |
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+---------------------+----------------+
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| Size | 16 MiB |
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+---------------------+----------------+
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| Package | SOIC-8 |
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+---------------------+----------------+
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| Write protection | no |
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+---------------------+----------------+
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| Dual BIOS feature | no |
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+---------------------+----------------+
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| Internal flashing | yes |
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+---------------------+----------------+
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```
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The flash IC is located between the PCH and the front panel connector,
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(circled) sometimes it is socketed.
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### How to flash
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Unlike ordinary desktop boards, the BIOS version 2.00 of X9SAE-V does not
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apply any write protection, so the main SPI flash can be accessed using
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[flashrom], and the whole flash is writable.
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Note: If you are going to modify the ME region via internal programming, you had
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better disable ME functionalities as much as possible in the vendor firmware
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first, otherwise ME may write something back and break the firmware you write.
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The following command may be used to flash coreboot. (To do so, linux kernel
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could be started with `iomem=relaxed` or unload the `lpc_ich` kernel module)
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Now you can [flash internally](/flash_tutorial/int_flashrom.md). It is
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recommended to flash only the `bios` region (use `--ifd -i bios -N` flashrom
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arguments), in order to minimize the chances of messing something up in the
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beginning.
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The flash chip is a SOIC-8 SPI flash, and may be socketed, so it's also easy
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to do in-system programming, or remove and flash externally if it is socketed.
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## Difference between X9SAE and X9SAE-V
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On X9SAE PCI-E slot 4 is absent. Lane 9~16 of PCI-E slot 6 on X9SAE are wired
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to slot 4 on X9SAE-V. Unlike ASUS P8C WS, there is no dynamic switch on X9SAE-V,
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so on X9SAE-V slot 6 can work as x8 at most.
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On X9SAE-V device pci 01.1 appears even if not defined in devicetree.cb, so it
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seems that it shall not appear on X9SAE even if it is defined.
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## Working (on my X9SAE-V)
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- Intel Xeon E3-1225 V2 with 4 M391B1G73BH0-YK0 UDIMMs, ECC confirmed active
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- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.46
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- Use PS/2 keyboard and mouse simutaneously with a PS/2 Y-cable
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- Both Onboard NIC
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- S3 Suspend to RAM
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- USB2 on rear and front panel connectors
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- USB3
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- Integrated SATA
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- CPU Temp sensors (tested PSensor on GNU/Linux)
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- LPC TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12)
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- Native raminit
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- Integrated graphics with libgfxinit
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- Nvidia Quadro 600 in all PCIe-16x slots
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- Compex WLM200NX (Qualcomm Atheros AR9220) in PCI slot
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- Debug output from serial port
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## Untested
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- EHCI debugging
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- S/PDIF audio
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- PS/2 mouse
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | bd82x6x |
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+------------------+--------------------------------------------------+
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| CPU | model_206ax |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6776F |
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+------------------+--------------------------------------------------+
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| EC | None |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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## Extra resources
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- [Flash chip datasheet][W25Q128FVSG]
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[X9SAE]: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae.cfm
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[X9SAE-V]: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae-v.cfm
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[W25Q128FVSG]: https://static.chipdip.ru/lib/093/DOC001093213.pdf
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[flashrom]: https://flashrom.org/Flashrom
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