coreboot-kgpe-d16/src/soc/nvidia/tegra132/Kconfig

config SOC_NVIDIA_TEGRA132
	bool
	default n
	select ARCH_BOOTBLOCK_ARMV4
	select ARCH_VERSTAGE_ARMV4
	select ARCH_ROMSTAGE_ARMV8_64
	select ARCH_RAMSTAGE_ARMV8_64
	select ARM_LPAE
	select DYNAMIC_CBMEM

if SOC_NVIDIA_TEGRA132

config BOOTBLOCK_ROM_OFFSET
	hex
	default 0x0

config CBFS_HEADER_ROM_OFFSET
	hex "offset of master CBFS header in ROM"
	default 0x18000

config CBFS_ROM_OFFSET
	hex "offset of CBFS data in ROM"
	default 0x18080

endif
tegra132: Add support for tegra132 soc Add basic support for tegra132 soc. BUG=None BRANCH=None TEST=Compiles successfully for rush board using tegra132 soc Original-Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197398 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 4746bff6e9f4b20abc44d0b6fce9691aea63583c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Reviewed-on: http://review.coreboot.org/8040 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> 2014-04-29 01:43:07 +02:00			`config SOC_NVIDIA_TEGRA132`
			`bool`
			`default n`
			`select ARCH_BOOTBLOCK_ARMV4`
tegra132: Fix build for verstage Verstage isn't included yet, but we need to have the Kconfig option for toolchain.inc to pass. Change-Id: I7fae73cd3b77fd347398221489caf745274701eb Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8409 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com> 2015-01-28 06:15:46 +01:00			`select ARCH_VERSTAGE_ARMV4`
tegra132: Add support for tegra132 soc Add basic support for tegra132 soc. BUG=None BRANCH=None TEST=Compiles successfully for rush board using tegra132 soc Original-Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197398 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 4746bff6e9f4b20abc44d0b6fce9691aea63583c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Reviewed-on: http://review.coreboot.org/8040 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> 2014-04-29 01:43:07 +02:00			`select ARCH_ROMSTAGE_ARMV8_64`
			`select ARCH_RAMSTAGE_ARMV8_64`
			`select ARM_LPAE`
			`select DYNAMIC_CBMEM`

			`if SOC_NVIDIA_TEGRA132`

			`config BOOTBLOCK_ROM_OFFSET`
			`hex`
			`default 0x0`

			`config CBFS_HEADER_ROM_OFFSET`
			`hex "offset of master CBFS header in ROM"`
			`default 0x18000`

			`config CBFS_ROM_OFFSET`
			`hex "offset of CBFS data in ROM"`
			`default 0x18080`

			`endif`