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coreboot-kgpe-d16/src/soc/intel/xeon_sp/Makefile.inc

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src: Replace remaining GPLv2 long form headers with SPDX header Change-Id: I4614e9b02a932530fc22912b5cf502d1b699b451 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-09 13:22:30 +02:00
## SPDX-License-Identifier: GPL-2.0-or-later
soc/intel: Add Intel Xeon Scalable Processor support This patch adds support for Intel Xeon-SP. This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base. The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-16 20:16:45 +01:00
soc/intel/xeon_sp: Refactor code to allow for additional CPUs types Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17 06:46:57 +01:00
ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
soc/intel: Add Intel Xeon Scalable Processor support This patch adds support for Intel Xeon-SP. This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base. The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-16 20:16:45 +01:00
soc/intel/xeon_sp: Refactor code to allow for additional CPUs types Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17 06:46:57 +01:00
subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx
soc/intel/xeon_sp: Add basic Cooperlake-SP support This adds barebones support. What works: * Linux kernel boots fine * SIRQ and PCH interupts work fine (only in IOAPIC mode) * PCH devices are usable What doesn't: * MP init is not there yet, only 1 CPU is up * SMM is not supported * GPIO is not available * All IIO and extended bus numbers enumeration is not yet available * Warm reset flow is untested * MRC cache save/load TEST=boots into Linux Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I7c987badc3c53f16ad178369c7e0906d6596e465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39713 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20 20:08:32 +01:00
subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
soc/intel: Add Intel Xeon Scalable Processor support This patch adds support for Intel Xeon-SP. This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base. The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-16 20:16:45 +01:00
soc/intel/xeon_sp: Early programming of ACPI bar ACPI bar was not programmed previously for which is needed to enable SMI's and to check SMI status registers. The architecture of Lewisburg PCH is very similar to SunrisePoint PCH thus we can use code from soc/intel/skylake. TEST=build for Tiogapass and check ACPI base. Log message will now show pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing to io port 0x500. Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379 Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-05-24 05:29:00 +02:00
bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
soc/intel/xeon_sp: Add a smm_region function This reports where TSEG is located and will be used when setting up SMM. Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-22 14:03:46 +02:00
romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c
soc/intel/xeon_sp: Use common cpu/intel romstage entry This removes some boilerplate like starting the console and also adds a "start of romstage" timestamp. Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-22 14:13:14 +02:00
romstage-y += ../../../cpu/intel/car/romstage.c
soc/intel/xeon_sp: Use common block ACPI Use the common block ACPI to further reduce the duplicate code. Change-Id: If28d75cbb2a88363d70e3ae6a2cace46cb6bbbab Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48248 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 19:33:02 +01:00
ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c ramstage.c chip_common.c
soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes coreboot in control of these settings. Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-12 21:17:56 +01:00
ramstage-y += memmap.c pch.c
soc/intel/xeon_sp: Enable PMC support PMC support was not enabled on Xeon_sp platforms. This involves turning on SOC_INTEL_COMMON_BLOCK_PMC and then adding the proper hooks in SOC specific code. This patch leverages code from the Skylake project and adds the bare minimum hooks to leverage PMC common code. Most importantly this enables power management registers located in the PMC device (under ACPI_BASE_ADDRESS). Access to this device is also needed for SMM setup and handling. TEST=build for Tiogapass and enable the following Kconfig options: select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select CPU_INTEL_COMMON_SMM Boot the system and ensure pmbase is programmed. (Look for pmbase in debug messages). Secondly check that SMIs are enabled by looking at the debug messages (search for "Enabling SMIs") and verifying in HW by reading IO port 0x530. Change-Id: I6d57a8282a8b6dc4314f156c39deb09535575cbd Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-06-11 20:18:02 +02:00
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
soc/intel/xeon_sp: Use common block ACPI Use the common block ACPI to further reduce the duplicate code. Change-Id: If28d75cbb2a88363d70e3ae6a2cace46cb6bbbab Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48248 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02 19:33:02 +01:00
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += nb_acpi.c acpi.c
soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM MSR save state are not supported, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. NOTE: - Code for accessing a CPU save state is not working for SMMLOADERV2, so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS pointer are not supported. - This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS is broken and needs to be fixed separately. It is unknown if TCO is supported. This might require a cleanup in the future. Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura@fb.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08 22:32:41 +02:00
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c pmc.c
soc/intel: Add Intel Xeon Scalable Processor support This patch adds support for Intel Xeon-SP. This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base. The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-16 20:16:45 +01:00
postcar-y += spi.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include
CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
soc/intel/xeon_sp: Refactor code to allow for additional CPUs types Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17 06:46:57 +01:00
endif ## XEON_SP_COMMON_BASE
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