GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
coreboot-kgpe-d16/Documentation/mainboard/sifive/hifive-unleashed.md

104 lines
3.6 KiB
Markdown
Raw Normal View History

Documentation: Add HiFive Unleashed documentation Change-Id: Ic97955e36feeaa18b5a0dbd502c722c06dcc1b31 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-19 16:23:55 +02:00
# SiFive HiFive Unleashed
This page describes how to run coreboot on the [HiFive Unleashed] development
board from [SiFive], the first RISC-V board on the market with enough resources
to run a multiuser operating system.
For general setup instructions, please refer to the [Getting Started Guide].
## TODO
The following things are still missing from this coreboot port:
riscv: add trampoline in MBR block to support boot mode 1 Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock. Tested on hardware: boot mode 15: works as before boot mode 1: jump to bootblock works, but bootblock needs to be modified to move the stack to L2LIM. This will be in a separate commit. Further changes are needed in the bootblock Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-07-07 15:54:37 +02:00
- Support running romstage from flash (fix stack) to support boot mode 1
Documentation: Add HiFive Unleashed documentation Change-Id: Ic97955e36feeaa18b5a0dbd502c722c06dcc1b31 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-19 16:23:55 +02:00
- CBMEM support
- FU540 clock configuration
- FU540 RAM init
- Placing the ramstage in DRAM
- Starting the U54 cores
- FU540 PIN configuration and GPIO access macros
soc/sifive/fu540: Add driver for OTP memory Provides minimal functionality to read the SOC s/n from the NeoFuse one time programmable memory. Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-07-11 13:22:34 +02:00
- Provide serial number to payload (e.g. in device tree)
Documentation: Add HiFive Unleashed documentation Change-Id: Ic97955e36feeaa18b5a0dbd502c722c06dcc1b31 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-19 16:23:55 +02:00
- Support for booting Linux on RISC-V
## Configuration
Run `make menuconfig` and select _SiFive_/_HiFive Unleashed_ in the _Mainboard_
menu.
### Boot modes
A total of 16 boot modes can be configured using the switches labeled `MSEL0`
through `MSEL3`. The most important ones are as follows:
- **MSEL=1**: Jump directly into the SPI flash, bypassing ROM1
- **MSEL=11**: Load FSBL from SD-card
- **MSEL=15**: Default boot mode; Load FSBL/coreboot from a GPT partition on
SPI flash
## Flashing coreboot
The HiFive Unleashed has an 32 MiB SPI flash (**ISSI IS25WP256D**), that can be
programmed from within Linux running on the board, via USB/JTAG, or directly
with an SPI programmer.
### Internal programming
The SPI flash can be accessed as `/dev/mtd0` from Linux.
### USB/JTAG
To program the flash via USB/JTAG, connect the USB port to a computer. If the
board is powered on, two new serial ports, for example `/dev/ttyUSB0` and
`/dev/ttyUSB1` will appear. The first is JTAG, and the second is connected to
the SoC's UART.
- Download and build the [RISC-V fork of OpenOCD].
- Download the [OpenOCD script] for Freedom Unleashed.
- Start OpenOCD with `openocd -f openocd.cfg`
- Connect to OpenOCD's command interface (via telnet) and enter the line
marked with `> `:
```
> flash write_image erase unlock build/coreboot.rom 0x20000000
auto erase enabled
auto unlock enabled
wrote 33554432 bytes from file build/coreboot.rom in 1524.943848s (21.488 KiB/s)
```
Note that programming the whole flash with OpenOCD isn't fast. In this
example it took just over 25 minutes. This process can be sped up
considerably by building/flashing a smaller image; OpenOCD does not check if
the image and the flash have the same size.
### External programming
External programming with an SPI adapter and [flashrom] may work, but has not
been tested. Please study the [schematics] before going this route.
## Error codes
The zeroth-stage bootloader (ZSBL) in ROM1 can print error codes on the serial
console in certain situations.
```
// Error codes are formatted as follows:
// [63:60] [59:56] [55:0]
// bootstage trap errorcode
// If trap == 1, then errorcode is actually the mcause register with the
// interrupt bit shifted to bit 55.
```
(--- from the [SiFive forum](https://forums.sifive.com/t/loading-fsbl-from-sd/1156/4))
[HiFive Unleashed]: https://www.crowdsupply.com/sifive/hifive-unleashed
[SiFive]: https://www.sifive.com/
Documentation/mb/sifive: Fix dead links SiFive's website was reorganized, which broke our links to PDF files. Update these links to the current ones, obtained by browsing https://sifive.com/documentation/. Change-Id: I312de84bf12abb0789bdd971c40033f1e4ea0dd1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-06 00:35:41 +02:00
[Getting Started Guide]: https://sifive.cdn.prismic.io/sifive%2Ffa3a584a-a02f-4fda-b758-a2def05f49f9_hifive-unleashed-getting-started-guide-v1p1.pdf
Documentation: Add HiFive Unleashed documentation Change-Id: Ic97955e36feeaa18b5a0dbd502c722c06dcc1b31 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-19 16:23:55 +02:00
[RISC-V fork of OpenOCD]: https://github.com/riscv/riscv-openocd
[OpenOCD script]: https://github.com/sifive/freedom-u-sdk/blob/057a47f657fa33e2c60df7f183884a68e90381cc/bsp/env/freedom-u500-unleashed/openocd.cfg
[flashrom]: https://flashrom.org/Flashrom
Documentation/mb/sifive: Fix dead links SiFive's website was reorganized, which broke our links to PDF files. Update these links to the current ones, obtained by browsing https://sifive.com/documentation/. Change-Id: I312de84bf12abb0789bdd971c40033f1e4ea0dd1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-10-06 00:35:41 +02:00
[schematics]: https://sifive.cdn.prismic.io/sifive%2Ff7173056-bf37-4407-87cb-d5ab76abf61a_hifive-unleashed-a00-schematics.pdf