riscv: add trampoline in MBR block to support boot mode 1
Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock. Tested on hardware: boot mode 15: works as before boot mode 1: jump to bootblock works, but bootblock needs to be modified to move the stack to L2LIM. This will be in a separate commit. Further changes are needed in the bootblock Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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@ -11,7 +11,7 @@ For general setup instructions, please refer to the [Getting Started Guide].
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The following things are still missing from this coreboot port:
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- Trampoline in the MBR block to support boot mode 1
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- Support running romstage from flash (fix stack) to support boot mode 1
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- CBMEM support
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- FU540 clock configuration
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- FU540 RAM init
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@ -25,6 +25,12 @@ BLOCK_MASK = BLOCK_SIZE - 1
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# Size of the bootcode part of the MBR
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MBR_BOOTCODE_SIZE = 0x1be
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# MBR trampoline to bootblock
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MBR_BOOTCODE = bytes([
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# j pc + 0x0800
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0x6f, 0x00, 0x10, 0x00,
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])
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# A protecive MBR, without the bootcode part
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PROTECTIVE_MBR_FOOTER = bytes([
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0x00, 0x00, 0x02, 0x00, 0xee, 0xff, 0xff, 0xff,
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@ -43,7 +49,7 @@ PROTECTIVE_MBR_FOOTER = bytes([
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# [1]: https://en.wikipedia.org/wiki/GUID_Partition_Table#PROTECTIVE-MBR
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class ProtectiveMBR:
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def __init__(self):
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self.bootcode = bytes(MBR_BOOTCODE_SIZE)
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self.bootcode = MBR_BOOTCODE + bytes(MBR_BOOTCODE_SIZE - len(MBR_BOOTCODE))
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def generate(self, stream):
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assert len(self.bootcode) == MBR_BOOTCODE_SIZE
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@ -177,5 +183,11 @@ if __name__ == '__main__':
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image.fixup()
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# Verify if first partition is at expected lba, otherwise trampoline will
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# fail
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if image.partitions[0].first_lba != 4:
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print('Warning: First partition not at expected location (LBA 4)')
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sys.exit(1)
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with open(sys.argv[2], 'wb') as f:
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image.generate(f)
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