115 lines
3 KiB
C
115 lines
3 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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* Copyright (C) 2013 Sage Electronic Engineering, LLC
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* Copyright (C) 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_def.h>
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#include <BiosCallOuts.h>
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#include <soc/southbridge.h>
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#include <agesawrapper.h>
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#include <amdlib.h>
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#include <dimmSpd.h>
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AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
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{
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AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams_reset;
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FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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FchParams_reset->FchReset.SataEnable = sb_sata_enable();
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FchParams_reset->FchReset.IdeEnable = sb_ide_enable();
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/* Get platform specific configuration changes */
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platform_FchParams_reset(FchParams_reset);
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printk(BIOS_DEBUG, "Done\n");
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}
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return AGESA_SUCCESS;
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}
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AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
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{
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AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
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if (StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
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oem_fan_control(FchParams_env);
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/* XHCI configuration */
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if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE))
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FchParams_env->Usb.Xhci0Enable = TRUE;
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else
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FchParams_env->Usb.Xhci0Enable = FALSE;
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FchParams_env->Usb.Xhci1Enable = FALSE;
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/* 8: If USB3 port is unremoveable. */
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FchParams_env->Usb.USB30PortInit = 8;
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/* SATA configuration */
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FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
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switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) {
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case SataRaid:
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case SataAhci:
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case SataAhci7804:
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case SataLegacyIde:
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FchParams_env->Sata.SataIdeMode = FALSE;
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break;
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case SataIde2Ahci:
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case SataIde2Ahci7804:
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default: /* SataNativeIde */
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FchParams_env->Sata.SataIdeMode = TRUE;
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break;
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}
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/* Platform updates */
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platform_FchParams_env(FchParams_env);
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printk(BIOS_DEBUG, "Done\n");
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}
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return AGESA_SUCCESS;
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}
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AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
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{
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AGESA_STATUS Status = AGESA_UNSUPPORTED;
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if (!ENV_ROMSTAGE)
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return Status;
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if (IS_ENABLED(CONFIG_GENERIC_SPD_BIN)) {
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AGESA_READ_SPD_PARAMS *info = ConfigPtr;
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if (info->MemChannelId > 0)
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return AGESA_UNSUPPORTED;
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if (info->SocketId != 0)
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return AGESA_UNSUPPORTED;
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if (info->DimmId > 1)
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return AGESA_UNSUPPORTED;
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die("SPD in cbfs not yet supported.\n");
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} else {
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Status = AmdMemoryReadSPD(Func, Data, ConfigPtr);
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}
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return Status;
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}
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