284 lines
8.7 KiB
C
284 lines
8.7 KiB
C
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <soc/tz.h>
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#define TZPC_TZPCR0SIZE 0x18034000
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#define TZPC_TZPCR0SIZE_MASK 0x000003ff
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#define TZPC_TZPCDECPROT0SET 0x18034804
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#define TZPC_TZPCDECPROT0CLR 0x18034808
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#define TZPC_TZPCDECPROT1SET 0x18034810
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#define TZPC_TZPCDECPROT1CLR 0x18034814
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#define TZPC_TZPCDECPROT2SET 0x1803481c
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#define TZPC_TZPCDECPROT2CLR 0x18034820
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#define TZPCDECPROT0_MASK 0x000000FF
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#define TZPCDECPROT1_MASK 0x000000FF
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#define TZPCDECPROT2_MASK 0x000000FF
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#define AXIIC_Ihost_acp_security 0x1a000008
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#define AXIIC_PCIe0_s0_security 0x1a000010
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#define AXIIC_PCIe1_s0_security 0x1a000014
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#define AXIIC_APBY_s0_security 0x1a00002c
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#define AXIIC_APBZ_s0_security 0x1a000030
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#define AXIIC_APBX_s0_security 0x1a000034
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#define AXIIC_ihost_s0_security 0x1a000038
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#define AXIIC_A9jtag_s0_security 0x1a00003c
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#define AXIIC_APB_W1_security 0x1a000040
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#define AXIIC_APB_W2_security 0x1a000044
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#define AXIIC_APB_W3_security 0x1a000048
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#define AXIIC_APB_W4_security 0x1a00004c
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#define AXIIC_APBR_s0_security 0x1a00006c
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#define AXIIC_APBS_s0_security 0x1a000070
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#define AXIIC_CMICd_s0_security 0x1a000074
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#define AXIIC_mhost0_s0_security 0x1a000078
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#define AXIIC_mhost1_s0_security 0x1a00007c
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#define AXIIC_Crypto_s0_security 0x1a000080
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#define AXIIC_DMU_s0_security 0x1a000084
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#define AXIIC_ext_s0_security 0x1a000088
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#define AXIIC_ext_s1_security 0x1a00008c
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#define AXIIC_APBY_s0_security_MASK 0x00003f1f
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#define AXIIC_APBZ_s0_security_MASK 0x0000003f
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#define AXIIC_APBX_s0_security_MASK 0x0000cfff
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#define AXIIC_ext_s0_security_MASK 0xffffffff
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#define AXIIC_ext_s1_security_MASK 0xffffffff
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#define AXIIC_APBR_s0_security_MASK 0x0000436d
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#define AXIIC_APBS_s0_security_MASK 0x000057ee
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#define AXIIC_APB_W1_security_MASK 0x0000ffff
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#define AXIIC_APB_W2_security_MASK 0x0000000f
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#define AXIIC_APB_W3_security_MASK 0x00003fff
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#define AXIIC_APB_W4_security_MASK 0x0000007f
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/*
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* Note: the order need to match corresponding definitions for
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* non virtual slave slave_vector in tz.h
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*/
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static uint32_t non_virtual_slave_regs[] = {
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AXIIC_Ihost_acp_security,
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AXIIC_PCIe0_s0_security,
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AXIIC_PCIe1_s0_security,
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AXIIC_ihost_s0_security,
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AXIIC_A9jtag_s0_security,
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AXIIC_CMICd_s0_security,
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AXIIC_mhost0_s0_security,
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AXIIC_mhost1_s0_security,
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AXIIC_Crypto_s0_security,
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AXIIC_DMU_s0_security
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};
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/*
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* Set master security.
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* Use defines in tz.h for both parameters.
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*/
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void tz_set_masters_security(uint32_t masters, uint32_t ns_bit)
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{
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uint32_t val;
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/* Check any TZPCDECPROT0 is set and then write to TZPCDECPROT0 */
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if (masters & TZPCDECPROT0_MASK) {
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val = masters & TZPCDECPROT0_MASK;
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if (ns_bit)
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write32((void *)TZPC_TZPCDECPROT0SET, val);
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else
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write32((void *)TZPC_TZPCDECPROT0CLR, val);
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}
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/* Check any TZPCDECPROT1 is set and then write to TZPCDECPROT1 */
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if ((masters >> 8) & TZPCDECPROT1_MASK) {
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val = (masters >> 8) & TZPCDECPROT1_MASK;
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if (ns_bit)
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write32((void *)TZPC_TZPCDECPROT1SET, val);
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else
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write32((void *)TZPC_TZPCDECPROT1CLR, val);
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}
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/* Check any TZPCDECPROT2 is set and then write to TZPCDECPROT2 */
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if ((masters >> 16) & TZPCDECPROT2_MASK) {
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val = (masters >> 16) & TZPCDECPROT2_MASK;
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if (ns_bit)
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write32((void *)TZPC_TZPCDECPROT2SET, val);
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else
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write32((void *)TZPC_TZPCDECPROT2CLR, val);
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}
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}
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/*
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* Set non virtual slave security.
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* Use defines in tz.h for both parameters.
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*/
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void tz_set_non_virtual_slaves_security(uint32_t slave_vector, uint32_t ns_bit)
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{
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uint32_t i;
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uint32_t total = sizeof(non_virtual_slave_regs) /
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sizeof(non_virtual_slave_regs[0]);
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uint32_t mask = ~(0xffffffff << total);
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ns_bit &= 0x1;
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slave_vector = slave_vector & mask;
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for (i = 0; i < total; i++) {
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if (slave_vector & (0x1 << i))
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write32((void *)(non_virtual_slave_regs[i]), ns_bit);
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}
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}
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/*
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* Set peripheral security.
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* Use defines in tz.h for both parameters.
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*/
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void tz_set_periph_security(uint32_t slave_vector, uint32_t ns_bit)
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{
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uint32_t val;
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uint32_t mask_x = AXIIC_APBX_s0_security_MASK;
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uint32_t mask_y = AXIIC_APBY_s0_security_MASK;
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uint32_t tz_periphs_sec_status =
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(mask_x & read32((void *)AXIIC_APBX_s0_security)) |
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((mask_y & read32((void *)AXIIC_APBY_s0_security)) << 16);
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if (ns_bit == TZ_STATE_SECURE)
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tz_periphs_sec_status &= ~slave_vector;
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else
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tz_periphs_sec_status |= slave_vector;
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val = tz_periphs_sec_status & mask_x;
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write32((void *)AXIIC_APBX_s0_security, val);
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val = (tz_periphs_sec_status >> 16) & mask_y;
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write32((void *)AXIIC_APBY_s0_security, val);
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}
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/*
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* Set sec peripheral security.
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* Use defines in tz.h for both parameters.
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*/
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void tz_set_sec_periphs_security(uint32_t slave_vector, uint32_t ns_bit)
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{
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uint32_t val;
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uint32_t mask = AXIIC_APBZ_s0_security_MASK;
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uint32_t tz_sec_periphs_sec_status =
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read32((void *)AXIIC_APBZ_s0_security);
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if (ns_bit == TZ_STATE_SECURE)
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tz_sec_periphs_sec_status &= ~slave_vector;
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else
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tz_sec_periphs_sec_status |= slave_vector;
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val = tz_sec_periphs_sec_status & mask;
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write32((void *)AXIIC_APBZ_s0_security, val);
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}
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/*
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* Set external slave security.
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* Use defines in tz.h for both parameters.
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*/
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void tz_set_ext_slaves_security(uint32_t slave_vector, uint32_t ns_bit)
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{
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uint32_t val;
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uint32_t mask_s0 = AXIIC_ext_s0_security_MASK;
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uint32_t mask_s1 = AXIIC_ext_s1_security_MASK;
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uint32_t tz_ext_slaves_sec_status =
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(mask_s0 & read32((void *)AXIIC_ext_s0_security)) |
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((mask_s1 & read32((void *)AXIIC_ext_s0_security)) << 16);
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if (ns_bit == TZ_STATE_SECURE)
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tz_ext_slaves_sec_status &= ~slave_vector;
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else
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tz_ext_slaves_sec_status |= slave_vector;
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val = tz_ext_slaves_sec_status & mask_s0;
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write32((void *)AXIIC_ext_s0_security, val);
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val = (tz_ext_slaves_sec_status >> 16) & mask_s1;
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write32((void *)AXIIC_ext_s1_security, val);
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}
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/*
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* Set cfg slave security
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* Use defines in tz.h for both parameters.
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*/
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void tz_set_cfg_slaves_security(uint32_t slave_vector, uint32_t ns_bit)
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{
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uint32_t val;
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uint32_t mask_r = AXIIC_APBR_s0_security_MASK;
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uint32_t mask_s = AXIIC_APBS_s0_security_MASK;
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uint32_t tz_cfg_slaves_sec_status =
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(mask_r & read32((void *)AXIIC_APBR_s0_security)) |
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((mask_s & read32((void *)AXIIC_APBS_s0_security)) << 16);
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if (ns_bit == TZ_STATE_SECURE)
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tz_cfg_slaves_sec_status &= ~slave_vector;
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else
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tz_cfg_slaves_sec_status |= slave_vector;
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val = tz_cfg_slaves_sec_status & mask_r;
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write32((void *)AXIIC_APBR_s0_security, val);
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val = (tz_cfg_slaves_sec_status >> 16) & mask_s;
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write32((void *)AXIIC_APBS_s0_security, val);
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}
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/*
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* Set SRAM secure region
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* parameter 'r0size' specify the secure RAM region in 4KB steps:
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* 0x00000000 = no secure region
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* 0x00000001 = 4KB secure region
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* 0x00000002 = 8KB secure region
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* .......
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* 0x000001FF = 2044KB secure region.
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* 0x00000200 or above sets the entire SRAM to secure regardless of size
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*/
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void tz_set_sram_sec_region(uint32_t r0size)
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{
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uint32_t mask = TZPC_TZPCR0SIZE_MASK;
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write32((void *)TZPC_TZPCR0SIZE, r0size & mask);
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}
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/*
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* Set wrapper security
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* Use defines in tz.h for all parameters.
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*/
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void tz_set_wrapper_security(uint32_t wrapper1, uint32_t wrapper2,
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uint32_t wrapper3, uint32_t wrapper4,
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uint32_t ns_bit)
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{
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uint32_t mask_w4 = AXIIC_APB_W4_security_MASK;
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uint32_t mask_w3 = AXIIC_APB_W3_security_MASK;
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uint32_t mask_w2 = AXIIC_APB_W2_security_MASK;
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uint32_t mask_w1 = AXIIC_APB_W1_security_MASK;
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uint32_t tz_wrapper1_sec_status = read32((void *)AXIIC_APB_W1_security);
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uint32_t tz_wrapper2_sec_status = read32((void *)AXIIC_APB_W2_security);
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uint32_t tz_wrapper3_sec_status = read32((void *)AXIIC_APB_W3_security);
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uint32_t tz_wrapper4_sec_status = read32((void *)AXIIC_APB_W4_security);
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if (ns_bit == TZ_STATE_SECURE) {
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tz_wrapper1_sec_status &= ~wrapper1;
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tz_wrapper2_sec_status &= ~wrapper2;
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tz_wrapper3_sec_status &= ~wrapper3;
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tz_wrapper4_sec_status &= ~wrapper4;
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} else {
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tz_wrapper1_sec_status |= wrapper1;
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tz_wrapper2_sec_status |= wrapper2;
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tz_wrapper3_sec_status |= wrapper3;
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tz_wrapper4_sec_status |= wrapper4;
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}
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write32((void *)AXIIC_APB_W1_security,
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tz_wrapper1_sec_status & mask_w1);
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write32((void *)AXIIC_APB_W2_security,
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tz_wrapper2_sec_status & mask_w2);
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write32((void *)AXIIC_APB_W3_security,
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tz_wrapper3_sec_status & mask_w3);
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write32((void *)AXIIC_APB_W4_security,
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tz_wrapper4_sec_status & mask_w4);
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}
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