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This is the final set of changes to allow rumba to build. Rumba is not tested. I also addressed questions raised by Uwe: TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 UDELAY_TSC Are now defined as booleans in src/cpu/x86/Kconfig and can be selected in the mainboard Kconfig. The remaining question of Uwe's is a deeper problem: --- We'll have to check if this works. From a quick glance the Rumba does not have the mmx related lines (which _are_ in Makefile.romccboard.inc, though): crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc crt0-y += auto.inc crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc --- We're going to need a whole variant of this standard mainboard OR we're going to have to make (some) of the unconditional includes above conditional. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-29 04:59:35 +02:00
source src/northbridge/amd/amdk8/Kconfig
Add initial kconfig support for all AMD GX1 boards. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04 19:15:39 +02:00
source src/northbridge/amd/gx1/Kconfig
This is the final set of changes to allow rumba to build. Rumba is not tested. I also addressed questions raised by Uwe: TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 UDELAY_TSC Are now defined as booleans in src/cpu/x86/Kconfig and can be selected in the mainboard Kconfig. The remaining question of Uwe's is a deeper problem: --- We'll have to check if this works. From a quick glance the Rumba does not have the mmx related lines (which _are_ in Makefile.romccboard.inc, though): crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc crt0-y += auto.inc crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc --- We're going to need a whole variant of this standard mainboard OR we're going to have to make (some) of the unconditional includes above conditional. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-29 04:59:35 +02:00
source src/northbridge/amd/gx2/Kconfig
some progress on kconfig: - northbridges are done - southbridges are done - Intel CPUs are done, with a design that the board only has to specify the socket it has, and the CPUs are pulled in automatically. There is some more cleanup possible in that area, but I'll do that later - a couple more mainboards compile: - intel/eagleheights - intel/jarrell - intel/mtarvon - intel/truxton - intel/xe7501devkit - sunw/ultra40 - supermicro/h8dme - tyan/s2850 - tyan/s2875 - via/epia - via/epia-cn - via/epia-m - via/epia-m700 - via/epia-n - via/pc2500e (PPC not considered, probably overlooked something) All of them only _build_, but some options are probably completely wrong. To be fixed later Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25 20:43:02 +02:00
source src/northbridge/amd/amdfam10/Kconfig
More kconfig: AMD LX AMD SC520 boards by iei, pcengines, technexion, technologic, thomson Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08 16:31:56 +02:00
source src/northbridge/amd/lx/Kconfig
Rename {CPU|NB|SB}/amd/*_wrapper folders This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-21 02:38:49 +02:00
source src/northbridge/amd/agesa/Kconfig
Move Kconfig for HT limits to northbridge/amd/Kconfig. Guard the code with CONFIG_EXPERT to remove warnings. Make it only show up for fam10, since it isn't implemented for K8 yet. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-08 17:02:39 +02:00
menu "HyperTransport setup"
#could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8)
depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
choice
prompt "HyperTransport frequency"
default LIMIT_HT_SPEED_AUTO
help
This option sets the maximum permissible HyperTransport link
frequency.
Use of this option will only limit the autodetected HT frequency.
It will not (and cannot) increase the frequency beyond the
autodetected limits.
This is primarily used to work around poorly designed or laid out
HT traces on certain motherboards.
config LIMIT_HT_SPEED_200
bool "Limit HT frequency to 200MHz"
Add 300 MHz and 500 MHz HT frequency limits Needed to build successfully with Expert mode enabled. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27 03:48:41 +01:00
config LIMIT_HT_SPEED_300
bool "Limit HT frequency to 300MHz"
Move Kconfig for HT limits to northbridge/amd/Kconfig. Guard the code with CONFIG_EXPERT to remove warnings. Make it only show up for fam10, since it isn't implemented for K8 yet. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-08 17:02:39 +02:00
config LIMIT_HT_SPEED_400
bool "Limit HT frequency to 400MHz"
Add 300 MHz and 500 MHz HT frequency limits Needed to build successfully with Expert mode enabled. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27 03:48:41 +01:00
config LIMIT_HT_SPEED_500
bool "Limit HT frequency to 500MHz"
Move Kconfig for HT limits to northbridge/amd/Kconfig. Guard the code with CONFIG_EXPERT to remove warnings. Make it only show up for fam10, since it isn't implemented for K8 yet. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-08 17:02:39 +02:00
config LIMIT_HT_SPEED_600
bool "Limit HT frequency to 600MHz"
config LIMIT_HT_SPEED_800
bool "Limit HT frequency to 800MHz"
config LIMIT_HT_SPEED_1000
bool "Limit HT frequency to 1.0GHz"
config LIMIT_HT_SPEED_1200
bool "Limit HT frequency to 1.2GHz"
config LIMIT_HT_SPEED_1400
bool "Limit HT frequency to 1.4GHz"
config LIMIT_HT_SPEED_1600
bool "Limit HT frequency to 1.6GHz"
config LIMIT_HT_SPEED_1800
bool "Limit HT frequency to 1.8GHz"
config LIMIT_HT_SPEED_2000
bool "Limit HT frequency to 2.0GHz"
config LIMIT_HT_SPEED_2200
bool "Limit HT frequency to 2.2GHz"
config LIMIT_HT_SPEED_2400
bool "Limit HT frequency to 2.4GHz"
config LIMIT_HT_SPEED_2600
bool "Limit HT frequency to 2.6GHz"
config LIMIT_HT_SPEED_AUTO
bool "Autodetect HT frequency"
endchoice
choice
prompt "HyperTransport downlink width"
default LIMIT_HT_DOWN_WIDTH_16
help
This option sets the maximum permissible HyperTransport
downlink width.
Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.
This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.
config LIMIT_HT_DOWN_WIDTH_8
bool "8 bits"
config LIMIT_HT_DOWN_WIDTH_16
bool "16 bits"
endchoice
choice
prompt "HyperTransport uplink width"
default LIMIT_HT_UP_WIDTH_16
help
This option sets the maximum permissible HyperTransport
uplink width.
Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.
This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.
config LIMIT_HT_UP_WIDTH_8
bool "8 bits"
config LIMIT_HT_UP_WIDTH_16
bool "16 bits"
endchoice
endmenu
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