2004-01-12 21:00:43 +01:00
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses MAINBOARD
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uses ARCH
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2004-03-24 15:10:45 +01:00
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uses HARD_RESET_BUS
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uses HARD_RESET_DEVICE
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uses HARD_RESET_FUNCTION
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2004-01-12 21:00:43 +01:00
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#
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#
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###
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### Set all of the defaults for an x86 architecture
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###
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#
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#
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###
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### Build the objects we have code for in this directory.
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###
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##object mainboard.o
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config chip.h
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register "fixup_scsi" = "1"
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register "fixup_vga" = "1"
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driver mainboard.o
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driver adaptec_scsi.o
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driver promise_sata.o
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driver intel_nic.o
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driver broadcom_nic.o
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2004-03-24 15:10:45 +01:00
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#object reset.o
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2004-01-12 21:00:43 +01:00
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#object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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2004-03-24 15:10:45 +01:00
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default HARD_RESET_BUS=1
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default HARD_RESET_DEVICE=2
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default HARD_RESET_FUNCTION=0
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#
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2004-01-12 21:00:43 +01:00
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arch i386 end
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#cpu k8 end
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#
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###
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### Build our 16 bit and 32 bit linuxBIOS entry code
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###
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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#
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###
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### Build our reset vector (This is where linuxBIOS is entered)
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###
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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else
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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#
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#### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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#
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###
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### Include an id string (For safe flashing)
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###
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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#
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####
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#### This is the early phase of linuxBIOS startup
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#### Things are delicate and we test to see if we should
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#### failover to another image.
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####
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#option MAX_REBOOT_CNT=2
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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#
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###
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### Setup our mtrrs
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###
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mainboardinit cpu/k8/earlymtrr.inc
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###
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### Only the bootstrap cpu makes it here.
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### Failover if we need to
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###
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#
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if USE_FALLBACK_IMAGE
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mainboardinit ./failover.inc
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end
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|
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|
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#
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|
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#
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###
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### Setup the serial port
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###
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#mainboardinit superiowinbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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#
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####
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|
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#### O.k. We aren't just an intermediary anymore!
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####
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|
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|
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#
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|
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|
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###
|
|
|
|
|
### When debugging disable the watchdog timer
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|
|
###
|
|
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|
|
##option MAXIMUM_CONSOLE_LOGLEVEL=7
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|
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#default MAXIMUM_CONSOLE_LOGLEVEL=7
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#
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#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
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|
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#
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|
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###
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|
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|
|
### Romcc output
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|
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|
|
###
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|
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|
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#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
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#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
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#mainboardinit .failover.inc
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makerule ./failover.E
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|
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depends "$(MAINBOARD)/failover.c"
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|
|
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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|
|
|
end
|
|
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|
|
|
|
|
|
|
makerule ./failover.inc
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|
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depends "./romcc ./failover.E"
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|
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
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|
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|
|
makerule ./auto.E
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|
|
depends "$(MAINBOARD)/auto.c"
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|
|
|
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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|
|
|
|
end
|
|
|
|
|
makerule ./auto.inc
|
|
|
|
|
depends "./romcc ./auto.E"
|
|
|
|
|
action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
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|
|
|
|
# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
|
|
|
|
|
end
|
|
|
|
|
mainboardinit cpu/k8/enable_mmx_sse.inc
|
|
|
|
|
mainboardinit ./auto.inc
|
|
|
|
|
mainboardinit cpu/k8/disable_mmx_sse.inc
|
|
|
|
|
#
|
|
|
|
|
###
|
|
|
|
|
### Include the secondary Configuration files
|
|
|
|
|
###
|
|
|
|
|
northbridge amd/amdk8 "mc0"
|
|
|
|
|
pci 0:18.0
|
|
|
|
|
pci 0:18.0
|
|
|
|
|
pci 0:18.0
|
|
|
|
|
pci 0:18.1
|
|
|
|
|
pci 0:18.2
|
|
|
|
|
pci 0:18.3
|
|
|
|
|
southbridge amd/amd8111 "amd8111" link 0
|
|
|
|
|
pci 0:0.0
|
|
|
|
|
pci 0:1.0 on
|
|
|
|
|
pci 0:1.1 on
|
|
|
|
|
pci 0:1.2 on
|
|
|
|
|
pci 0:1.3 on
|
|
|
|
|
pci 0:1.5 off
|
|
|
|
|
pci 0:1.6 off
|
|
|
|
|
pci 1:0.0 on
|
|
|
|
|
pci 1:0.1 on
|
|
|
|
|
pci 1:0.2 on
|
|
|
|
|
pci 1:1.0 off
|
|
|
|
|
end
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
#northbridge amd/amdk8
|
|
|
|
|
#end
|
|
|
|
|
#southbridge amd/amd8111 "amd8111"
|
|
|
|
|
#end
|
|
|
|
|
#mainboardinit archi386/smp/secondary.inc
|
|
|
|
|
#superio NSC/pc87360
|
|
|
|
|
# register "com1" = "{1}"
|
|
|
|
|
# register "lpt" = "{1}"
|
|
|
|
|
#end
|
|
|
|
|
dir /pc80
|
|
|
|
|
##dir /src/superio/winbond/w83627hf
|
|
|
|
|
#dir /bioscall
|
|
|
|
|
#dir /cpu/k8
|
|
|
|
|
cpu k8 "cpu0"
|
|
|
|
|
register "up" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}"
|
|
|
|
|
end
|
|
|
|
|
|
