2015-05-12 01:45:56 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cache.h>
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2015-05-28 21:13:51 +02:00
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#include <arch/lib_helpers.h>
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2015-10-08 03:38:24 +02:00
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#include <arch/mmu.h>
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2015-05-28 21:13:51 +02:00
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#include <arch/transition.h>
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2015-05-12 01:45:56 +02:00
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#include <arm_tf.h>
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#include <assert.h>
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#include <cbfs.h>
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#include <cbmem.h>
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2018-04-21 22:45:32 +02:00
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#include <compiler.h>
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2015-05-16 06:39:23 +02:00
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#include <program_loading.h>
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2015-05-12 01:45:56 +02:00
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/*
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* TODO: Many of these structures are currently unused. Better not fill them out
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* to make future changes fail fast, rather than try to come up with content
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* that might turn out to not make sense. Implement later as required.
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*
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static image_info_t bl31_image_info;
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static image_info_t bl32_image_info;
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static image_info_t bl33_image_info;
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*/
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2015-05-28 21:13:51 +02:00
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static entry_point_info_t bl32_ep_info;
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2015-05-12 01:45:56 +02:00
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static entry_point_info_t bl33_ep_info;
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static bl31_params_t bl31_params;
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2018-04-21 22:45:32 +02:00
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void __weak *soc_get_bl31_plat_params(bl31_params_t *params)
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2015-05-20 20:03:50 +02:00
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{
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/* Default weak implementation. */
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return NULL;
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}
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2015-05-12 01:45:56 +02:00
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void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
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{
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2015-12-08 21:34:35 +01:00
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struct prog bl31 = PROG_INIT(PROG_BL31, CONFIG_CBFS_PREFIX"/bl31");
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2015-05-12 01:45:56 +02:00
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void (*bl31_entry)(bl31_params_t *params, void *plat_params) = NULL;
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2015-05-16 06:39:23 +02:00
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if (prog_locate(&bl31))
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die("BL31 not found");
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arm64: Use 'payload' format for ATF instead of 'stage'
Switch the BL31 (ARM Trusted Firmware) format to payload so that it can
have multiple independent segments. This also requires disabling the region
check since SRAM is currently faulted by that check.
This has been tested with Rockchip's pending change:
https://chromium-review.googlesource.com/#/c/368592/3
with the patch mentioned on the bug at #13.
BUG=chrome-os-partner:56314
BRANCH=none
TEST=boot on gru and see that BL31 loads and runs. Im not sure if it is
correct though:
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 1b440 size 15a75
Loading segment from ROM address 0x0000000000100000
code (compression=1)
New segment dstaddr 0x18104800 memsize 0x117fbe0 srcaddr 0x100038 filesize 0x15a3d
Loading segment from ROM address 0x000000000010001c
Entry Point 0x0000000018104800
Loading Segment: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d
using LZMA
[ 0x18104800, 18137d90, 0x192843e0) <- 00100038
Clearing Segment: addr: 0x0000000018137d90 memsz: 0x000000000114c650
dest 0000000018104800, end 00000000192843e0, bouncebuffer ffffffffffffffff
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 125150 exit 1
Jumping to boot code at 0000000018104800(00000000f7eda000)
CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8ef3d0, stack used: 3120 bytes
CBFS: 'VBOOT' located CBFS at [402000:44cc00)
CBFS: Locating 'fallback/bl31'
CBFS: Found @ offset 10ec0 size 8d0c
Loading segment from ROM address 0x0000000000100000
code (compression=1)
New segment dstaddr 0x10000 memsize 0x40000 srcaddr 0x100054 filesize 0x8192
Loading segment from ROM address 0x000000000010001c
code (compression=1)
New segment dstaddr 0xff8d4000 memsize 0x1f50 srcaddr 0x1081e6 filesize 0xb26
Loading segment from ROM address 0x0000000000100038
Entry Point 0x0000000000010000
Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192
using LZMA
[ 0x00010000, 00035708, 0x00050000) <- 00100054
Clearing Segment: addr: 0x0000000000035708 memsz: 0x000000000001a8f8
dest 0000000000010000, end 0000000000050000, bouncebuffer ffffffffffffffff
Loading Segment: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26
lb: [0x0000000000300000, 0x0000000000320558)
Post relocation: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26
using LZMA
[ 0xff8d4000, ff8d5f50, 0xff8d5f50) <- 001081e6
dest 00000000ff8d4000, end 00000000ff8d5f50, bouncebuffer ffffffffffffffff
Loaded segments
INFO: plat_rockchip_pmusram_prepare pmu: code d2bfe625,d2bfe625,80
INFO: plat_rockchip_pmusram_prepare pmu: code 0xff8d4000,0x50000,3364
INFO: plat_rockchip_pmusram_prepare: data 0xff8d4d28,0xff8d4d24,4648
NOTICE: BL31: v1.2(debug):
NOTICE: BL31: Built : Sun Sep 4 22:36:16 UTC 2016
INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3
INFO: plat_rockchip_pmu_init(1189): pd status 3e
INFO: BL31: Initializing runtime services
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x18104800
INFO: SPSR = 0x8
Change-Id: Ie2484d122a603f1c7b7082a1de3f240aa6e6d540
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c1d75bff6e810a39776048ad9049ec0a9c5d94e
Original-Change-Id: I2d60e5762f8377e43835558f76a3928156acb26c
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376849
Original-Commit-Ready: Simon Glass <sjg@google.com>
Original-Tested-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16706
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-27 20:18:38 +02:00
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bl31_entry = selfload(&bl31, false);
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if (!bl31_entry)
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2015-05-16 06:39:23 +02:00
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die("BL31 load failed");
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2015-05-12 01:45:56 +02:00
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SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0);
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2015-05-28 21:13:51 +02:00
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if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_OS)) {
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2016-08-27 20:02:09 +02:00
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struct prog bl32 = PROG_INIT(PROG_BL32,
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CONFIG_CBFS_PREFIX"/secure_os");
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2015-05-28 21:13:51 +02:00
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if (prog_locate(&bl32))
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2016-08-27 20:02:09 +02:00
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die("BL32 not found");
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2015-05-28 21:13:51 +02:00
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if (cbfs_prog_stage_load(&bl32))
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2016-08-27 20:02:09 +02:00
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die("BL32 load failed");
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2015-05-28 21:13:51 +02:00
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2016-08-27 20:02:09 +02:00
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SET_PARAM_HEAD(&bl32_ep_info, PARAM_EP, VERSION_1,
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PARAM_EP_SECURE);
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2015-05-28 21:13:51 +02:00
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bl32_ep_info.pc = (uintptr_t)prog_entry(&bl32);
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2016-08-27 20:02:09 +02:00
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bl32_ep_info.spsr = SPSR_EXCEPTION_MASK |
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get_eret_el(EL1, SPSR_USE_L);
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2015-05-28 21:13:51 +02:00
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bl31_params.bl32_ep_info = &bl32_ep_info;
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}
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2015-05-12 01:45:56 +02:00
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bl31_params.bl33_ep_info = &bl33_ep_info;
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SET_PARAM_HEAD(&bl33_ep_info, PARAM_EP, VERSION_1, PARAM_EP_NON_SECURE);
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bl33_ep_info.pc = payload_entry;
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bl33_ep_info.spsr = payload_spsr;
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bl33_ep_info.args.arg0 = payload_arg0;
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2017-07-25 22:55:43 +02:00
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/* May update bl31_params if necessary. */
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2015-05-12 01:45:56 +02:00
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void *bl31_plat_params = soc_get_bl31_plat_params(&bl31_params);
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2017-07-25 22:55:43 +02:00
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/* MMU disable will flush cache, so passed params land in memory. */
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arch/arm64: Use correct SPSR.DAIF mask for BL31 and payload
The PSTATE mask bits for Debug exceptions, external Aborts, Interrupts
and Fast interrupts are usually best left unset: under normal
circumstances none of those exceptions should occur in firmware, and if
they do it's better to get a crash close to the code that caused it
(rather than much later when the kernel first unmasks them). For this
reason arm64_cpu_init unmasks them right after boot. However, the EL2
payload was still running with all mask bits set, which this patch
fixes.
BL31, on the other hand, explicitly wants to be entered with all masks
set (see calling convention in docs/firmware-design.md), which we had
previously not been doing. It doesn't seem to make a difference at the
moment, but since it's explicitly specified we should probably comply.
BRANCH=None
BUG=None
TEST=Booted Oak, confirmed with raw_read_daif() in payload that mask
bits are now cleared.
Change-Id: I04406da4c435ae7d44e2592c41f9807934bbc802
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ba55bc23fbde962d91c87dc0f982437572a69a8
Original-Change-Id: Ic5fbdd4e1cd7933c8b0c7c5fe72eac2022c9553c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/325056
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13596
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-02 04:47:10 +01:00
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raw_write_daif(SPSR_EXCEPTION_MASK);
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2015-10-08 03:38:24 +02:00
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mmu_disable();
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2015-05-12 01:45:56 +02:00
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bl31_entry(&bl31_params, bl31_plat_params);
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die("BL31 returned!");
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}
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