2020-04-05 15:46:41 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2013-09-07 07:41:48 +02:00
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/* The devicetree parser expects chip.h to reside directly in the path
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* specified by the devicetree. */
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2013-10-29 00:15:02 +01:00
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#ifndef _BAYTRAIL_CHIP_H_
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#define _BAYTRAIL_CHIP_H_
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2018-01-29 01:42:10 +01:00
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#include <drivers/intel/gma/i915.h>
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2013-10-29 00:15:02 +01:00
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#include <stdint.h>
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2013-09-07 07:41:48 +02:00
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struct soc_intel_baytrail_config {
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2014-02-22 21:26:55 +01:00
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uint8_t enable_xdp_tap;
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uint8_t sata_port_map;
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uint8_t sata_ahci;
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uint8_t ide_legacy_combined;
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2013-11-22 21:16:49 +01:00
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uint8_t clkreq_enable;
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2013-11-01 21:32:53 +01:00
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2014-01-17 02:52:21 +01:00
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/* VR low power settings -- enable PS2 mode for gfx and core */
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int vnn_ps2_enable;
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int vcc_ps2_enable;
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/* Disable SLP_X stretching after SUS power well loss. */
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int disable_slp_x_stretch_sus_fail;
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2013-11-01 21:32:53 +01:00
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/* USB Port Disable mask */
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uint16_t usb2_port_disable_mask;
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uint16_t usb3_port_disable_mask;
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/* USB routing */
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int usb_route_to_xhci;
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2013-11-01 21:34:00 +01:00
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/* USB PHY settings specific to the board */
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uint32_t usb2_per_port_lane0;
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uint32_t usb2_per_port_rcomp_hs_pullup0;
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uint32_t usb2_per_port_lane1;
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uint32_t usb2_per_port_rcomp_hs_pullup1;
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uint32_t usb2_per_port_lane2;
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uint32_t usb2_per_port_rcomp_hs_pullup2;
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uint32_t usb2_per_port_lane3;
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uint32_t usb2_per_port_rcomp_hs_pullup3;
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2014-07-17 18:51:50 +02:00
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uint32_t usb2_comp_bg;
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2013-12-04 18:03:20 +01:00
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/* LPE Audio Clock configuration. */
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int lpe_codec_clk_freq; /* 19 or 25 are valid. */
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int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
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2013-12-10 17:35:51 +01:00
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/* Native SD Card controller - override controller capabilities. */
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uint32_t sdcard_cap_low;
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uint32_t sdcard_cap_high;
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2013-12-09 23:38:57 +01:00
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2013-12-10 23:37:42 +01:00
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/* Enable devices in ACPI mode */
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int lpss_acpi_mode;
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int scc_acpi_mode;
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int lpe_acpi_mode;
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2014-02-22 21:26:55 +01:00
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/* Allow PCIe devices to wake system from suspend. */
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int pcie_wake_enable;
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soc/intel/baytrail: Prevent unintended sign extensions
Consider the following assignment:
u64 = s32
For positive values this is fine, but if the s32 is negative, it will be
sign-extended in the conversion to a very large unsigned integer. This
manifests itself in two ways in the following code:
First, gpu_pipe{a,b}_port_select are defined as int, and can have the
values 1 or 2. In the case when they have the value 2, the shift 2 << 30
will be a negative number, making it susceptible to the sign-extension
problem above. Change these variables to something more reasonable like
a uint8_t, which is unsigned.
Second, in any bit shift, any variable with width less than an int will
be implicitly promoted to an int before performing the bit shift.
For example, the variable gpu_pipea_power_on_delay is a uint16_t, and if its
highest bit is set, the shift gpu_pipea_power_on_delay << 16 will become
negative, again introducing the above problem. To prevent this, cast all
smaller variables to a u32 before the shift, which will prevent the
implicit promotions and sign extensions.
Change-Id: Ic5db6001504cefb501dee199590a0e961a15771b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229699, 1229700, 1229701, 1229702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34487
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-22 21:31:38 +02:00
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uint8_t gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */
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2013-12-09 23:38:57 +01:00
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uint16_t gpu_pipea_power_on_delay;
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uint16_t gpu_pipea_light_on_delay;
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uint16_t gpu_pipea_power_off_delay;
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uint16_t gpu_pipea_light_off_delay;
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uint16_t gpu_pipea_power_cycle_delay;
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2014-04-24 18:35:28 +02:00
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int gpu_pipea_pwm_freq_hz;
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2013-12-09 23:38:57 +01:00
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soc/intel/baytrail: Prevent unintended sign extensions
Consider the following assignment:
u64 = s32
For positive values this is fine, but if the s32 is negative, it will be
sign-extended in the conversion to a very large unsigned integer. This
manifests itself in two ways in the following code:
First, gpu_pipe{a,b}_port_select are defined as int, and can have the
values 1 or 2. In the case when they have the value 2, the shift 2 << 30
will be a negative number, making it susceptible to the sign-extension
problem above. Change these variables to something more reasonable like
a uint8_t, which is unsigned.
Second, in any bit shift, any variable with width less than an int will
be implicitly promoted to an int before performing the bit shift.
For example, the variable gpu_pipea_power_on_delay is a uint16_t, and if its
highest bit is set, the shift gpu_pipea_power_on_delay << 16 will become
negative, again introducing the above problem. To prevent this, cast all
smaller variables to a u32 before the shift, which will prevent the
implicit promotions and sign extensions.
Change-Id: Ic5db6001504cefb501dee199590a0e961a15771b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229699, 1229700, 1229701, 1229702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34487
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-22 21:31:38 +02:00
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uint8_t gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */
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2013-12-09 23:38:57 +01:00
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uint16_t gpu_pipeb_power_on_delay;
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uint16_t gpu_pipeb_light_on_delay;
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uint16_t gpu_pipeb_power_off_delay;
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uint16_t gpu_pipeb_light_off_delay;
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uint16_t gpu_pipeb_power_cycle_delay;
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2014-04-24 18:35:28 +02:00
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int gpu_pipeb_pwm_freq_hz;
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2015-01-17 01:19:54 +01:00
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int disable_ddr_2x_refresh_rate;
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2018-01-29 01:42:10 +01:00
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struct i915_gpu_controller_info gfx;
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2013-09-07 07:41:48 +02:00
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};
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#endif /* _BAYTRAIL_CHIP_H_ */
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