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coreboot-kgpe-d16/src/cpu/samsung/exynos5250/Kconfig

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bootblock_cpu_init() stub for exynos5250 This adds a stub for bootblock_cpu_init() for exynos5250. It will eventually contain code to copy ROM content from SPI to SRAM. Change-Id: I26ee62a1e701013f38f76f200579faa680530860 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2138 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11 20:34:06 +01:00
config BOOTBLOCK_CPU_INIT
string
default "cpu/samsung/exynos5250/bootblock.c"
help
CPU/SoC-specific bootblock code. This is useful if the
bootblock must load microcode or copy data from ROM before
searching for the bootblock.
WIP: Initial support for Samsung Exynos 5250 ARM CPU Samsung SoC files, including Exynos5 (a Cortex-A15 implementation). Since this is an SoC we'll forego the x86-style {north,south}bridge and cpu distinction. We may try to split some stuff out before the final version if prudent. Change-Id: Ie068e9dc3dd836c83d90e282b10d5202e7a4ba9b Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2005 Tested-by: build bot (Jenkins)
2012-12-08 02:18:43 +01:00
config EXYNOS_ACE_SHA
bool
default n
config SATA_AHCI
bool
default n
config SPL_BUILD
bool
default n
config SYS_TEXT_BASE
hex "Executable code section"
default 0x43e00000
config SYS_SDRAM_BASE
hex "SDRAM base address"
default 0x40000000
#FIXME(dhendrix, reinauer): re-visit this RAMBASE/RAMTOP stuff...
config RAMBASE
hex
default SYS_SDRAM_BASE
# according to stefan, this is RAMBASE + 1M.
config RAMTOP
hex
default 0x40100000
move iRAM config variable to exynos5250 Kconfig Since these don't seem very generic and depend on the BL1, let's move them to the CPU-specific Kconfig. Change-Id: I33059b7db30d35a1853918a580f312e50a3499fa Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2077 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-27 22:50:32 +01:00
config IRAM_BOTTOM
hex
default 0x02020000
config IRAM_TOP
hex
default 0x02077fff
config SYS_INIT_SP_ADDR
hex
Snow bootblock (bloated/debug version) This is the bloated Snow bootblock which includes: - SPI driver - UART, including requisite I2C, Maxim PMIC, and clock config code. - Adjustments for magic offsets (id section, stack pointer address) This is just a temporary solution until we have romstage loading. Once that happens, we'll rip out all but the code necessary for copying SPI ROM content into SRAM. Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-18 00:07:35 +01:00
default 0x02058000
move iRAM config variable to exynos5250 Kconfig Since these don't seem very generic and depend on the BL1, let's move them to the CPU-specific Kconfig. Change-Id: I33059b7db30d35a1853918a580f312e50a3499fa Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2077 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-27 22:50:32 +01:00
config IRAM_STACK
hex
default SYS_INIT_SP_ADDR
config XIP_ROM_SIZE
hex "ROM stage (BL2) size"
default 0x20000
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