Snow bootblock (bloated/debug version)
This is the bloated Snow bootblock which includes: - SPI driver - UART, including requisite I2C, Maxim PMIC, and clock config code. - Adjustments for magic offsets (id section, stack pointer address) This is just a temporary solution until we have romstage loading. Once that happens, we'll rip out all but the code necessary for copying SPI ROM content into SRAM. Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -259,7 +259,7 @@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootbloc
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ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
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$(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld
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else
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$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $<
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$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $< $(LIBGCC_FILE_NAME) -Wl,--end-group
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endif
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################################################################################
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@ -40,6 +40,7 @@ void main(unsigned long bist)
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if (boot_cpu()) {
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bootblock_mainboard_init();
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bootblock_cpu_init();
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}
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entry = findstage(target1);
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@ -1,6 +1,6 @@
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SECTIONS {
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/* FIXME: determine a sensible location... */
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. = (0x2024000) - (__id_end - __id_start);
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. = (0x2026400);
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.id (.): {
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*(.id)
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}
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@ -35,11 +35,11 @@
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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/* ENTRY(_start) */
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SECTIONS
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{
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. = CONFIG_ROMSTAGE_BASE;
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. = 0x02023400 + 0x4000;
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.romtext . : {
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_rom = .;
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@ -45,7 +45,7 @@ config IRAM_TOP
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config SYS_INIT_SP_ADDR
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hex
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default 0x0204F800
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default 0x02058000
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config IRAM_STACK
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hex
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@ -17,16 +17,24 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if 0
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/*
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* Set/clear program flow prediction and return the previous state.
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*/
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static int config_branch_prediction(int set_cr_z)
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{
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unsigned int cr;
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/* System Control Register: 11th bit Z Branch prediction enable */
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cr = get_cr();
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set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
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return cr & CR_Z;
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}
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#endif
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void bootblock_cpu_init(void);
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void bootblock_cpu_init(void)
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{
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/*
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* FIXME: this is a stub for now. It should eventually copy
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* romstage data (and maybe more) from SPI to SRAM.
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*/
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#if 0
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volatile unsigned long *addr = (unsigned long *)0x1004330c;
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*addr |= 0x100;
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while (1) ;
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#endif
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/* FIXME: this is a stub for now */
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}
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@ -56,6 +56,10 @@ config MAINBOARD_VENDOR
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string
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default "Samsung"
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config BOOTBLOCK_MAINBOARD_INIT
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string
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default "mainboard/google/snow/bootblock.c"
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# SPL (second-phase loader) stuff
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config SPL_TEXT_BASE
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hex
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