fba42a793a
This is the bloated Snow bootblock which includes: - SPI driver - UART, including requisite I2C, Maxim PMIC, and clock config code. - Adjustments for magic offsets (id section, stack pointer address) This is just a temporary solution until we have romstage loading. Once that happens, we'll rip out all but the code necessary for copying SPI ROM content into SRAM. Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Google Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <bootblock_common.h>
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#include <arch/cbfs.h>
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#include <arch/hlt.h>
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static int boot_cpu(void)
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{
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/*
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* FIXME: This is a stub for now. All non-boot CPUs should be
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* waiting for an interrupt. We could move the chunk of assembly
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* which puts them to sleep in here...
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*/
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return 1;
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}
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void main(unsigned long bist)
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{
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const char *target1 = "fallback/romstage";
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unsigned long entry;
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if (boot_cpu()) {
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bootblock_mainboard_init();
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bootblock_cpu_init();
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}
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entry = findstage(target1);
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if (entry) call(entry);
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hlt();
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}
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