51 lines
1.1 KiB
C
51 lines
1.1 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/hlt.h>
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#include <arch/io.h>
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#include <reset.h>
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/* Reset control port */
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#define RST_CNT 0xcf9
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#define FULL_RST (1 << 3)
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#define RST_CPU (1 << 2)
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#define SYS_RST (1 << 1)
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void hard_reset(void)
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{
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/* S0->S5->S0 trip. */
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outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
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while (1)
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hlt();
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}
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void soft_reset(void)
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{
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/* PMC_PLTRST# asserted. */
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outb(RST_CPU | SYS_RST, RST_CNT);
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while (1)
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hlt();
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}
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void cpu_reset(void)
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{
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/* Sends INIT# to CPU */
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outb(RST_CPU, RST_CNT);
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while (1)
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hlt();
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}
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