soc/mediatek/mt8195: configure DMA buffer in DRAM

Set DRAM DMA to be non-cacheable to load blob correctly.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54052
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/mt8195/Makefile.inc

@@ -26,6 +26,7 @@ romstage-y += emi.c
 romstage-y += ../common/flash_controller.c
 romstage-y += ../common/gpio.c gpio.c
 romstage-y += ../common/i2c.c i2c.c
+romstage-y += ../common/mmu_operations.c mmu_operations.c
 romstage-y += ../common/pll.c pll.c
 romstage-y += scp.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c

src/soc/mediatek/mt8195/mmu_operations.c

@@ -29,3 +29,10 @@ void mtk_soc_disable_l2c_sram(void)
 			MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
 	dsb();
 }
+
+/* mtk_soc_after_dram is called in romstage */
+void mtk_soc_after_dram(void)
+{
+	mmu_config_range(_dram_dma, REGION_SIZE(dram_dma),
+			 NONSECURE_UNCACHED_MEM);
+}