soc/mediatek/mt8195: configure DMA buffer in DRAM

Set DRAM DMA to be non-cacheable to load blob correctly.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54052
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Rex-BC Chen 2021-05-10 20:06:35 +08:00 committed by Hung-Te Lin
parent 8c3b747ccf
commit 00b43c9843
2 changed files with 8 additions and 0 deletions

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@ -26,6 +26,7 @@ romstage-y += emi.c
romstage-y += ../common/flash_controller.c romstage-y += ../common/flash_controller.c
romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/gpio.c gpio.c
romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/i2c.c i2c.c
romstage-y += ../common/mmu_operations.c mmu_operations.c
romstage-y += ../common/pll.c pll.c romstage-y += ../common/pll.c pll.c
romstage-y += scp.c romstage-y += scp.c
romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c

View File

@ -29,3 +29,10 @@ void mtk_soc_disable_l2c_sram(void)
MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
dsb(); dsb();
} }
/* mtk_soc_after_dram is called in romstage */
void mtk_soc_after_dram(void)
{
mmu_config_range(_dram_dma, REGION_SIZE(dram_dma),
NONSECURE_UNCACHED_MEM);
}