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mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP 

ADL-M LP4 RVP has command mirror enabled and we need to fill correct
value of this UPD to pass the MRC.
Also, Value of TxDqDqsRetraining is set to 1 by default and we need to
disable it for only ADL-M LP5 RVP.

BUG=None
BRANCH=None
TEST=UPD values has been pass correctly and MRC passes on LP4/LP5 board

Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Maulik V Vaghela 2021-02-23 14:06:01 +05:30 committed by Felix Held
parent d1bf408da8
commit 01ecb77ef6
1 changed files with 12 additions and 0 deletions
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12
src/mainboard/intel/adlrvp/memory.c
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@ -20,6 +20,8 @@ static const struct mb_cfg ddr4_mem_config = {
.UserBd = BOARD_TYPE_MOBILE,
.LpDdrDqDqsReTraining = 1,
.ddr_config = {
.dq_pins_interleaved = false,
},
@ -76,6 +78,8 @@ static const struct mb_cfg lpddr4_mem_config = {
.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
},
.LpDdrDqDqsReTraining = 1,
.ect = true, /* Early Command Training */
.UserBd = BOARD_TYPE_MOBILE,
@ -134,6 +138,8 @@ static const struct mb_cfg lp5_mem_config = {
.ect = false, /* Early Command Training */
.LpDdrDqDqsReTraining = 1,
.UserBd = BOARD_TYPE_MOBILE,
.lp5x_config = {
@ -156,6 +162,8 @@ static const struct mb_cfg ddr5_mem_config = {
.UserBd = BOARD_TYPE_MOBILE,
.LpDdrDqDqsReTraining = 1,
.ddr_config = {
.dq_pins_interleaved = false,
}
@ -214,6 +222,10 @@ static const struct mb_cfg adlm_lp4_mem_config = {
.ect = true, /* Early Command Training */
.CmdMirror = 0xCC,
.LpDdrDqDqsReTraining = 1,
.UserBd = BOARD_TYPE_ULT_ULX,
};