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sb/intel/bd82x6x: Use array for PCIe ASPM overrides 

Using an array reduces the amount of boilerplate code.

Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55246
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-06-05 12:34:23 +02:00 committed by Patrick Georgi
parent d047927168
commit 023968453e
4 changed files with 4 additions and 36 deletions
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2
src/mainboard/google/butterfly/devicetree.cb
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@ -72,7 +72,7 @@ chip northbridge/intel/sandybridge
device pci 1c.1 on end # PCIe Port #2 (ETH0) device pci 1c.1 on end # PCIe Port #2 (ETH0)
device pci 1c.2 on end # PCIe Port #3 (Card Reader) device pci 1c.2 on end # PCIe Port #3 (Card Reader)
#force ASPM for PCIe bridge to Card Reader #force ASPM for PCIe bridge to Card Reader
register "pcie_aspm_f2" = "0x3" register "pcie_aspm[2]" = "0x3"
device pci 1c.3 off end # PCIe Port #4 device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5 device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6 device pci 1c.5 off end # PCIe Port #6

2
src/mainboard/google/stout/devicetree.cb
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@ -76,7 +76,7 @@ chip northbridge/intel/sandybridge
device pci 1c.0 on end # PCIe Port #1 device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2 (WLAN) device pci 1c.1 on end # PCIe Port #2 (WLAN)
device pci 1c.2 on end # PCIe Port #3 (Card Reader) device pci 1c.2 on end # PCIe Port #3 (Card Reader)
register "pcie_aspm_f2" = "0x3" register "pcie_aspm[2]" = "0x3"
device pci 1c.3 off end # PCIe Port #4 device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5 device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 on end # PCIe Port #6 (LAN) device pci 1c.5 on end # PCIe Port #6 (LAN)

9
src/southbridge/intel/bd82x6x/chip.h
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@ -61,14 +61,7 @@ struct southbridge_intel_bd82x6x_config {
uint8_t pcie_port_coalesce; uint8_t pcie_port_coalesce;
/* Override PCIe ASPM */ /* Override PCIe ASPM */
uint8_t pcie_aspm_f0; uint8_t pcie_aspm[8];
uint8_t pcie_aspm_f1;
uint8_t pcie_aspm_f2;
uint8_t pcie_aspm_f3;
uint8_t pcie_aspm_f4;
uint8_t pcie_aspm_f5;
uint8_t pcie_aspm_f6;
uint8_t pcie_aspm_f7;
int c2_latency; int c2_latency;
int docking_supported; int docking_supported;

27
src/southbridge/intel/bd82x6x/pcie.c
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@ -162,32 +162,7 @@ static void pch_pcie_pm_late(struct device *dev)
pci_or_config32(dev, 0xd4, 1 << 1); pci_or_config32(dev, 0xd4, 1 << 1);
/* Check for a rootport ASPM override */ /* Check for a rootport ASPM override */
switch (PCI_FUNC(dev->path.pci.devfn)) { apmc = config->pcie_aspm[PCI_FUNC(dev->path.pci.devfn)];
case 0:
apmc = config->pcie_aspm_f0;
break;
case 1:
apmc = config->pcie_aspm_f1;
break;
case 2:
apmc = config->pcie_aspm_f2;
break;
case 3:
apmc = config->pcie_aspm_f3;
break;
case 4:
apmc = config->pcie_aspm_f4;
break;
case 5:
apmc = config->pcie_aspm_f5;
break;
case 6:
apmc = config->pcie_aspm_f6;
break;
case 7:
apmc = config->pcie_aspm_f7;
break;
}
/* Setup the override or get the real ASPM setting */ /* Setup the override or get the real ASPM setting */
if (apmc) { if (apmc) {