mb/google/sarien: Update GPIOs for next build
Update the GPIOs for the next board build. Mostly minor changes but the polarity change on GPP_E8/RECOVERY on sarien will result in it booting to recovery every time unless using new hardware. For this reason the recovery mode GPIO that is passed to vboot is commented out for sarien. It is only used for testing and currently it is useful to have an image that works on both board versions. Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30062 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -30,18 +30,23 @@ static const struct pad_config gpio_table[] = {
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/* ESPI_CLK */
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/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE),
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/* PME# */ PAD_NC(GPP_A11, NONE),
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/* BM_BUSY# */ PAD_NC(GPP_A12, NONE),
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/* ISH_LID_CL#_TAB */
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/* BM_BUSY# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* SUSWARN# */ PAD_NC(GPP_A13, NONE),
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/* ESPI_RESET# */
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/* SUSACK# */ PAD_NC(GPP_A15, NONE),
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/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
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/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),
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/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),
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/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),
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/* ISH_ACC1_INT# */
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/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* ISH_ACC2_INT# */
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/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
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/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
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/* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
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/* ISH_GP4 */ PAD_NC(GPP_A22, NONE),
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/* ISH_GP5 */ PAD_NC(GPP_A23, NONE),
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/* ISH_NB_MODE */
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/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
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/* ISH_LID_CL#_NB */
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/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
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/* CORE_VID0 */
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/* CORE_VID1 */
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@ -49,12 +54,17 @@ static const struct pad_config gpio_table[] = {
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/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
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EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
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/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
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/* LAN_CLKREQ_CPU_N */
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/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* CARD_CLKREQ_CPU_N */
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/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* WLAN_CLKREQ_CPU_N */
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* WWAN_CLKREQ_CPU_N */
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/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* SSD_CKLREQ_CPU_N */
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/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),
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/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */
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/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */
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/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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@ -63,7 +73,7 @@ static const struct pad_config gpio_table[] = {
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/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */
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/* GSPI0_MISO */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */
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/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
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/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE),
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/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */
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/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
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/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
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/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
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@ -112,8 +122,10 @@ static const struct pad_config gpio_table[] = {
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/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE),
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/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */
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/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE),
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/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),
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/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),
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/* ISH_CPU_UART0_RX */
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/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* ISH_CPU_UART0_TX */
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/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
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/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */
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/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),
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/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */
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@ -144,10 +156,10 @@ static const struct pad_config gpio_table[] = {
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/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */
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/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */
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/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
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/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE),
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/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */
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/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
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/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
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/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */
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/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */
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/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),
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/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),
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/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
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@ -179,9 +191,9 @@ static const struct pad_config gpio_table[] = {
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/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE),
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/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */
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/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),
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/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */
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/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */
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/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */
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/* SD_DATA2 */ PAD_NC(GPP_G3, NONE),
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/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */
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/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */
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/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */
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@ -49,11 +49,11 @@ static const struct pad_config gpio_table[] = {
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/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
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EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
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/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
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/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */
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/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */
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/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */
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/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */
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/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),
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/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */
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/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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@ -63,8 +63,7 @@ static const struct pad_config gpio_table[] = {
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/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),
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/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),
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/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
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/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, PLTRST,
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EDGE_SINGLE, INVERT), /* HDD_FALL_INT */
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/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */
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/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
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/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
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/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
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@ -101,7 +100,7 @@ static const struct pad_config gpio_table[] = {
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EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */
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/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),
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/* SPI1_MISO */ PAD_NC(GPP_D2, NONE),
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/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE),
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/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* RTC_DET# */
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/* FASHTRIG */ PAD_NC(GPP_D4, NONE),
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/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),
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/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),
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@ -135,7 +134,7 @@ static const struct pad_config gpio_table[] = {
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/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */
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/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */
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/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */
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/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */
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/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
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/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */
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/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */
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/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */
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@ -143,8 +142,7 @@ static const struct pad_config gpio_table[] = {
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/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */
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/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */
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/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
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/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, PLTRST,
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EDGE_SINGLE, INVERT), /* FFS_INT2 */
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/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */
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/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
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/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
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@ -237,7 +235,7 @@ static const struct pad_config early_gpio_table[] = {
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/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */
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/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
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/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
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/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */
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/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
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/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
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};
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@ -254,7 +252,10 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AH(GPP_E8, CROS_GPIO_DEVICE_NAME),
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/*
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* TODO: re-enable recovery mode when boards are updated:
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* CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME),
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*/
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CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),
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};
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