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mb/google/sarien: Setup GPIOs again after FSP-S 

Currently CoffeeLake FSP is incorrectly modifying GPIO pad configuration
if specific UPD variables are not set as it expects.

This affects the display-related SOC pads with the following UPD variables:

UINT8 DdiPortBHpd; // GPP_E13
UINT8 DdiPortCHpd; // GPP_E14
UINT8 DdiPortDHpd; // GPP_E15
UINT8 DdiPortFHpd; // GPP_E16
UINT8 DdiPortBDdc; // GPP_E18/GPP_E19
UINT8 DdiPortCDdc; // GPP_E20/GPP_E21
UINT8 DdiPortDDdc; // GPP_E22/GPP_E23
UINT8 DdiPortFDdc; // GPP_H16/GPP_H17

Until FSP is fixed to not touch the pad configuration this workaround
will reprogram the GPIO settings after FSP-S step so they are correct
when the OS attempts to use them.

This was found in CoffeLake FSP Gold release:
https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg

As well as the current top-of-tree for the FSP sources.

BUG=b:120686247,chromium:913216
TEST=verify correct GPIO configuration for GPP_E group in the kernel

Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Duncan Laurie 2018-12-08 12:00:17 -08:00 committed by Patrick Georgi
parent f63c3f6448
commit 1a1f00cf41
1 changed files with 11 additions and 0 deletions
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11
src/mainboard/google/sarien/ramstage.c
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@ -27,8 +27,19 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
gpio_configure_pads(gpio_table, num_gpios);
}
/* Workaround FSP issue by reprogramming GPIOs after FSP-S */
static void mainboard_init(struct device *dev)
{
const struct pad_config *gpio_table;
size_t num_gpios;
gpio_table = variant_gpio_table(&num_gpios);
gpio_configure_pads(gpio_table, num_gpios);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}