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soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO boot 

A UPD HybridStorageMode allows a platform to dynamically configure the
PCIe strap configuration required if an Optane device is connected.
The strap configuration is done by HECI commands between FSP and CSE to
override the default PCIe strap value, and the updated strap value is
stored in SPI RW data to be used on the next boot.

CSE Lite supports the strap override when running on CSE RW partition,
while CSE RO partition does not support it because CSE RO is not allowed
to access SPI RW data. The strap override failure on CSE RO causes FSP
not initializing PCH Clkreq and PCIe port mapping and this results NVMe
and Optane initialization failure.

By disabling HybridStorageMode in case of CSE RO boot, NVMe detection is
done by the default PCIe configuration and Optane is detected as a
single NVMe storage device on CSE RO boot in recovery mode. Both NVMe
and Optane devices detection as well as OS installation to these storage
devices are verified on CSE RO boot in recovery mode.

BUG=b:158643194
TEST=boot and verified with tglrvp and volteer in recovery mode
Cq-Depend: chrome-internal:3100721

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42282
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jamie Ryu 2020-06-11 01:57:13 -07:00 committed by Nick Vaccaro
parent 401671c7ab
commit 02a1b338f8
1 changed files with 15 additions and 1 deletions
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14
src/soc/intel/tigerlake/fsp_params.c
View File

@ -7,9 +7,11 @@
#include <fsp/api.h> #include <fsp/api.h>
#include <fsp/ppi/mp_service_ppi.h> #include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h> #include <fsp/util.h>
#include <intelblocks/cse.h>
#include <intelblocks/lpss.h> #include <intelblocks/lpss.h>
#include <intelblocks/xdci.h> #include <intelblocks/xdci.h>
#include <intelpch/lockdown.h> #include <intelpch/lockdown.h>
#include <security/vboot/vboot_common.h>
#include <soc/gpio_soc_defs.h> #include <soc/gpio_soc_defs.h>
#include <soc/intel/common/vbt.h> #include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
@ -255,7 +257,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
/* Enable Hybrid storage auto detection */ /* Enable Hybrid storage auto detection */
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite()
&& vboot_recovery_mode_enabled() && !cse_is_hfs1_com_normal()) {
/*
* CSE Lite SKU does not support hybrid storage dynamic configuration
* in CSE RO boot, and FSP does not allow to send the strap override
* HECI commands if CSE is not in normal mode; hence, hybrid storage
* mode is disabled on CSE RO boot in recovery boot mode.
*/
printk(BIOS_INFO, "cse_lite: CSE RO boot. HybridStorageMode disabled\n");
params->HybridStorageMode = 0;
} else {
params->HybridStorageMode = config->HybridStorageMode; params->HybridStorageMode = config->HybridStorageMode;
}
/* USB4/TBT */ /* USB4/TBT */
for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {