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fsp_baytrail: use external microcode .h files 

The microcode for Bay Trail that's in the blobs repo is for the
M and D chip variants only.  The fsp_baytrail directory is for
Bay Trail I chip variants, and will not boot if the M/D microcode
is used.  The microcode for the I variant is supplied as part
of the Bay Trail FSP package.

Change-Id: I5493deb1626dc3cf037053e13e092f5a1143a13a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12334
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Martin Roth 2015-11-05 08:06:54 -07:00
parent 66a476ad5f
commit 0307e0a499
2 changed files with 7 additions and 2 deletions
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7
src/soc/intel/fsp_baytrail/Kconfig
View File

@ -46,6 +46,9 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
# Microcode header files are delivered in FSP package
select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
config SOC_INTEL_FSP_BAYTRAIL_MD
bool
default n
@ -98,6 +101,10 @@ config VGA_BIOS_FILE
string
default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS
config CPU_MICROCODE_HEADER_FILES
string
default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h"
## Baytrail Specific FSP Kconfig
source src/soc/intel/fsp_baytrail/fsp/Kconfig

2
src/soc/intel/fsp_baytrail/Makefile.inc
View File

@ -55,8 +55,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
ramstage-y += placeholders.c
ramstage-y += i2c.c
cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp