fsp_baytrail: use external microcode .h files
The microcode for Bay Trail that's in the blobs repo is for the M and D chip variants only. The fsp_baytrail directory is for Bay Trail I chip variants, and will not boot if the M/D microcode is used. The microcode for the I variant is supplied as part of the Bay Trail FSP package. Change-Id: I5493deb1626dc3cf037053e13e092f5a1143a13a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12334 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -46,6 +46,9 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_INTEL_FIRMWARE
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select HAVE_INTEL_FIRMWARE
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select HAVE_SPI_CONSOLE_SUPPORT
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select HAVE_SPI_CONSOLE_SUPPORT
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# Microcode header files are delivered in FSP package
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select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
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config SOC_INTEL_FSP_BAYTRAIL_MD
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config SOC_INTEL_FSP_BAYTRAIL_MD
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bool
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bool
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default n
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default n
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@ -98,6 +101,10 @@ config VGA_BIOS_FILE
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string
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string
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default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS
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default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS
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config CPU_MICROCODE_HEADER_FILES
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string
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default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h"
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## Baytrail Specific FSP Kconfig
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## Baytrail Specific FSP Kconfig
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source src/soc/intel/fsp_baytrail/fsp/Kconfig
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source src/soc/intel/fsp_baytrail/fsp/Kconfig
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@ -55,8 +55,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
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ramstage-y += placeholders.c
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ramstage-y += placeholders.c
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ramstage-y += i2c.c
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ramstage-y += i2c.c
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cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
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CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
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CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
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CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
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CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
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