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soc/amd/common/block/espi: Increase ESPI_CH_READY_TIMEOUT_US to 10ms 

The ChromeEC might take longer than 1ms for the peripheral channel to be
enabled. The PLTRST# interrupt handler takes about ~539us.
This doesn't account for the time it takes for the interrupt handler
to be scheduled. Increasing the timeout to 10ms gives ample time.

BUG=b:188188172, b:188935533
TEST=Boot guybrush and no longer see channel enable errors

Suggested-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib6db577bf06175ceb17b446af706ad8c9f891481
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54788
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel 2021-05-21 16:31:52 -06:00 committed by Raul Rangel
parent 0d93ca48c0
commit 0318dc169e
1 changed files with 1 additions and 1 deletions
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2
src/soc/amd/common/block/lpc/espi_util.c
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@ -371,7 +371,7 @@ enum espi_cmd_type {
#define ESPI_RXVW_POLARITY 0xac #define ESPI_RXVW_POLARITY 0xac
#define ESPI_CMD_TIMEOUT_US 100 #define ESPI_CMD_TIMEOUT_US 100
#define ESPI_CH_READY_TIMEOUT_US 1000 #define ESPI_CH_READY_TIMEOUT_US 10000
union espi_txhdr0 { union espi_txhdr0 {
uint32_t val; uint32_t val;