soc/amd/picasso: factor out AOAC offset defines
Factoring out those defines allows using them easily in the ACPI code without having to use preprocessor macros. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I99cb03de8782a0eeeb505f567b982099b0e8a18d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -3,6 +3,7 @@
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#include <stdint.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/aoac.h>
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#include <soc/aoac_defs.h>
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#include <soc/southbridge.h>
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#include <delay.h>
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@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef AMD_PICASSO_AOAC_DEFS_H
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#define AMD_PICASSO_AOAC_DEFS_H
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/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
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#define FCH_AOAC_DEV_CLK_GEN 0
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#define FCH_AOAC_DEV_I2C2 7
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#define FCH_AOAC_DEV_I2C3 8
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#define FCH_AOAC_DEV_I2C4 9
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#define FCH_AOAC_DEV_UART0 11
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#define FCH_AOAC_DEV_UART1 12
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#define FCH_AOAC_DEV_UART2 16
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#define FCH_AOAC_DEV_AMBA 17
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#define FCH_AOAC_DEV_UART3 26
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#define FCH_AOAC_DEV_ESPI 27
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#define FCH_AOAC_DEV_EMMC 28
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#endif /* AMD_PICASSO_AOAC_DEFS_H */
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@ -119,19 +119,6 @@
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#define I2C_PAD_CTRL_SPARE0 BIT(17)
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#define I2C_PAD_CTRL_SPARE1 BIT(18)
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/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
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#define FCH_AOAC_DEV_CLK_GEN 0
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#define FCH_AOAC_DEV_I2C2 7
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#define FCH_AOAC_DEV_I2C3 8
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#define FCH_AOAC_DEV_I2C4 9
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#define FCH_AOAC_DEV_UART0 11
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#define FCH_AOAC_DEV_UART1 12
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#define FCH_AOAC_DEV_UART2 16
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#define FCH_AOAC_DEV_AMBA 17
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#define FCH_AOAC_DEV_UART3 26
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#define FCH_AOAC_DEV_ESPI 27
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#define FCH_AOAC_DEV_EMMC 28
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#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
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/* SATA Controller D11F0 */
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@ -7,6 +7,7 @@
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#include <amdblocks/gpio_banks.h>
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#include <amdblocks/aoac.h>
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#include <amdblocks/uart.h>
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#include <soc/aoac_defs.h>
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#include <soc/southbridge.h>
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#include <soc/gpio.h>
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#include <soc/uart.h>
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