soc/amd/cezanne,picasso: add AOAC offset define for the eMMC controller

BUG=b:184978118

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I03554a151aa6a6d9e15d74c63cd02239b788808a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/cezanne/include/soc/southbridge.h

@@ -117,6 +117,7 @@
 #define FCH_AOAC_DEV_UART1		12
 #define FCH_AOAC_DEV_AMBA		17
 #define FCH_AOAC_DEV_ESPI		27
+#define FCH_AOAC_DEV_EMMC		28
 
 void fch_pre_init(void);
 void fch_early_init(void);

src/soc/amd/picasso/include/soc/southbridge.h

@@ -130,6 +130,7 @@
 #define FCH_AOAC_DEV_AMBA		17
 #define FCH_AOAC_DEV_UART3		26
 #define FCH_AOAC_DEV_ESPI		27
+#define FCH_AOAC_DEV_EMMC		28
 
 #define FCH_LEGACY_UART_DECODE		(ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */