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mb/google/brya/redrix{4es}: Disable unused USB2/TCSS ports 

Disable unused USB2/TCSS Ports.

BUG=b:217238553
TEST=FW_NAME=redrix emerge-brya coreboot

Change-Id: I1cdee5b6dc56accb52ba1bf636bdf753a7bfd199
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Wisley Chen 2022-02-17 15:53:06 +06:00 committed by Felix Held
parent 130de14a05
commit 03c0853f4d
2 changed files with 10 additions and 0 deletions
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5
src/mainboard/google/brya/variants/redrix/overridetree.cb
View File

@ -41,6 +41,11 @@ chip soc/intel/alderlake
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
register "usb2_ports[1]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_EMPTY"
register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |

5
src/mainboard/google/brya/variants/redrix4es/overridetree.cb
View File

@ -41,6 +41,11 @@ chip soc/intel/alderlake
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
register "usb2_ports[1]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_EMPTY"
register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |