soc/intel/cannonlake: Correct gpio definition

The following changes have been applied for GPIO:
1. Correct port id using by GPIO community 3 for CNL-LP.
2. Correct number of doubleword for each pad from 2 to 4.

Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/soc/intel/cannonlake/gpio.c

@@ -75,7 +75,7 @@ static const struct pad_community cnl_communities[] = {
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 	}, { /* GPP C, E */
-		.port = PID_GPIOCOM3,
+		.port = PID_GPIOCOM4,
 		.first_pad = GPP_C0,
 		.last_pad = GPP_E23,
 		.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,

src/soc/intel/cannonlake/include/soc/gpio_defs.h

@@ -22,7 +22,7 @@
 #include <soc/gpio_soc_defs.h>
 
 
-#define GPIO_NUM_PAD_CFG_REGS   2 /* DW0, DW1 */
+#define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
 
 #define NUM_GPIO_COMx_GPI_REGS(n)	\
 		(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)