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soc/intel/cannonlake: Correct gpio definition 

The following changes have been applied for GPIO:
1. Correct port id using by GPIO community 3 for CNL-LP.
2. Correct number of doubleword for each pad from 2 to 4.

Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Lijian Zhao 2017-07-25 18:42:29 -07:00 committed by Aaron Durbin
parent 1a4add9e87
commit 03e44f46b0
2 changed files with 2 additions and 2 deletions
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2
src/soc/intel/cannonlake/gpio.c
View File

@ -75,7 +75,7 @@ static const struct pad_community cnl_communities[] = {
.reset_map = rst_map, .reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map), .num_reset_vals = ARRAY_SIZE(rst_map),
}, { /* GPP C, E */ }, { /* GPP C, E */
.port = PID_GPIOCOM3, .port = PID_GPIOCOM4,
.first_pad = GPP_C0, .first_pad = GPP_C0,
.last_pad = GPP_E23, .last_pad = GPP_E23,
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,

2
src/soc/intel/cannonlake/include/soc/gpio_defs.h
View File

@ -22,7 +22,7 @@
#include <soc/gpio_soc_defs.h> #include <soc/gpio_soc_defs.h>
#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
#define NUM_GPIO_COMx_GPI_REGS(n) \ #define NUM_GPIO_COMx_GPI_REGS(n) \
(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)