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mainboard/google/kahlee: Add romstage GPIO initialization 

Move the backlight initialization from bootblock to romstage

BUG=b:120436919
TEST=Careena backlight is enabled

Change-Id: Ia4993b993d37afaf9e23d6f3316ba91053732f1d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Martin Roth 2018-12-04 15:16:00 -07:00 committed by Patrick Georgi
parent 822ffe1ef0
commit 03f05cff2f
3 changed files with 20 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/mainboard/google/kahlee/romstage.c
View File

@ -15,6 +15,7 @@
#include <amdblocks/dimm_spd.h> #include <amdblocks/dimm_spd.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <soc/gpio.h>
#include <soc/romstage.h> #include <soc/romstage.h>
int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len) int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len)
@ -29,5 +30,11 @@ void __weak variant_romstage_entry(int s3_resume)
void mainboard_romstage_entry(int s3_resume) void mainboard_romstage_entry(int s3_resume)
{ {
size_t num_gpios;
const struct soc_amd_gpio *gpios;
gpios = variant_romstage_gpio_table(&num_gpios);
sb_program_gpios(gpios, num_gpios);
variant_romstage_entry(s3_resume); variant_romstage_entry(s3_resume);
} }

15
src/mainboard/google/kahlee/variants/baseboard/gpio.c
View File

@ -77,9 +77,6 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* GPIO_132 - CONFIG_STRAP4 */ /* GPIO_132 - CONFIG_STRAP4 */
PAD_GPI(GPIO_132, PULL_NONE), PAD_GPI(GPIO_132, PULL_NONE),
/* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */
PAD_GPO(GPIO_133, HIGH),
/* GPIO_136 - UART_PCH_RX_DEBUG_TX */ /* GPIO_136 - UART_PCH_RX_DEBUG_TX */
PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
@ -93,6 +90,11 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
PAD_GPI(GPIO_142, PULL_NONE), PAD_GPI(GPIO_142, PULL_NONE),
}; };
static const struct soc_amd_gpio gpio_set_stage_rom[] = {
/* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */
PAD_GPO(GPIO_133, HIGH),
};
static const struct soc_amd_gpio gpio_set_stage_ram[] = { static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* GPIO_0 - EC_PCH_PWR_BTN_ODL */ /* GPIO_0 - EC_PCH_PWR_BTN_ODL */
PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP),
@ -258,6 +260,13 @@ struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
return gpio_set_stage_reset; return gpio_set_stage_reset;
} }
const __weak
struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(gpio_set_stage_rom);
return gpio_set_stage_rom;
}
const __weak const __weak
struct soc_amd_gpio *variant_gpio_table(size_t *size) struct soc_amd_gpio *variant_gpio_table(size_t *size)
{ {

1
src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
View File

@ -28,6 +28,7 @@ int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len);
int variant_get_xhci_oc_map(uint16_t *usb_oc_map); int variant_get_xhci_oc_map(uint16_t *usb_oc_map);
int variant_get_ehci_oc_map(uint16_t *usb_oc_map); int variant_get_ehci_oc_map(uint16_t *usb_oc_map);
const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
const struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size);
const struct soc_amd_gpio *variant_gpio_table(size_t *size); const struct soc_amd_gpio *variant_gpio_table(size_t *size);
void variant_romstage_entry(int s3_resume); void variant_romstage_entry(int s3_resume);
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)