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soc/amd/stoneyridge: Run romstage mainboard code before AGESA 

This is needed so the next patch can set up GPIOs before
AGESA runs.

BUG=b:120436919
TEST=Verified romstage mainboard code runs before AGESA

Change-Id: I76c035e166cd64382b52dff5ae00a6f115cbac9b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30038
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2018-12-04 15:08:56 -07:00 committed by Patrick Georgi
parent ad41f55123
commit 822ffe1ef0
1 changed files with 1 additions and 2 deletions
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3
src/soc/amd/stoneyridge/romstage.c
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@ -96,11 +96,10 @@ asmlinkage void car_stage_entry(void)
if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
load_smu_fw1();
mainboard_romstage_entry(s3_resume);
bsp_agesa_call();
mainboard_romstage_entry(s3_resume);
if (!s3_resume) {
post_code(0x40);
do_agesawrapper(agesawrapper_amdinitpost, "amdinitpost");