haswell: Drop GPIO indirection layers
This simplifies things and makes type checking possible. Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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@ -72,7 +72,6 @@ void mainboard_romstage_entry(void)
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struct romstage_params romstage_params = {
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.pei_data = &pei_data,
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.gpio_map = &mainboard_gpio_map,
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};
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romstage_common(&romstage_params);
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@ -72,7 +72,6 @@ void mainboard_romstage_entry(void)
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struct romstage_params romstage_params = {
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.pei_data = &pei_data,
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.gpio_map = &mainboard_gpio_map,
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};
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romstage_common(&romstage_params);
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@ -11,8 +11,6 @@
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#include <superio/ite/it8772f/it8772f.h>
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#include "onboard.h"
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extern const struct pch_lp_gpio_map mainboard_gpio_map[];
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void mainboard_config_rcba(void)
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{
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/*
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@ -107,7 +105,6 @@ void mainboard_romstage_entry(void)
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struct romstage_params romstage_params = {
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.pei_data = &pei_data,
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.gpio_map = &mainboard_gpio_map,
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};
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/* Early SuperIO setup */
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@ -8,8 +8,6 @@
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#include <southbridge/intel/lynxpoint/lp_gpio.h>
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#include "variant.h"
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extern const struct pch_lp_gpio_map mainboard_gpio_map[];
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void mainboard_config_rcba(void)
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{
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/*
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@ -77,7 +75,6 @@ void mainboard_romstage_entry(void)
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struct romstage_params romstage_params = {
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.pei_data = &pei_data,
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.gpio_map = &mainboard_gpio_map,
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};
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variant_romstage_entry(&romstage_params);
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@ -114,7 +114,6 @@ void mainboard_romstage_entry(void)
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struct romstage_params romstage_params = {
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.pei_data = &pei_data,
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.gpio_map = &mainboard_gpio_map,
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.copy_spd = NULL,
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};
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@ -74,7 +74,6 @@ void mainboard_romstage_entry(void)
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struct romstage_params romstage_params = {
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.pei_data = &pei_data,
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.gpio_map = &mainboard_gpio_map,
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};
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romstage_common(&romstage_params);
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@ -70,7 +70,6 @@ void mainboard_romstage_entry(void)
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struct romstage_params romstage_params = {
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.pei_data = &pei_data,
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.gpio_map = &mainboard_gpio_map,
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};
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romstage_common(&romstage_params);
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@ -192,7 +192,6 @@ void intel_northbridge_haswell_finalize_smm(void);
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struct pei_data;
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struct romstage_params {
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struct pei_data *pei_data;
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const void *gpio_map;
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void (*copy_spd)(struct pei_data *peid);
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};
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void romstage_common(const struct romstage_params *params);
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@ -19,7 +19,7 @@ void romstage_common(const struct romstage_params *params)
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enable_lapic();
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wake_from_s3 = early_pch_init(params->gpio_map);
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wake_from_s3 = early_pch_init();
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/* Perform some early chipset initialization required
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* before RAM initialization can work
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@ -13,6 +13,7 @@
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#if CONFIG(INTEL_LYNXPOINT_LP)
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#include "lp_gpio.h"
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extern const struct pch_lp_gpio_map mainboard_gpio_map[];
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#else
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#include <southbridge/intel/common/gpio.h>
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#endif
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@ -77,16 +78,16 @@ void __weak mainboard_config_superio(void)
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{
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}
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int early_pch_init(const void *gpio_map)
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int early_pch_init(void)
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{
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int wake_from_s3;
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pch_enable_bars();
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#if CONFIG(INTEL_LYNXPOINT_LP)
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setup_pch_lp_gpios(gpio_map);
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setup_pch_lp_gpios(mainboard_gpio_map);
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#else
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setup_pch_gpios(gpio_map);
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setup_pch_gpios(&mainboard_gpio_map);
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#endif
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pch_generic_setup();
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@ -121,7 +121,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet);
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void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
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void enable_usb_bar(void);
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int early_pch_init(const void *gpio_map);
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int early_pch_init(void);
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void pch_enable_lpc(void);
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void mainboard_config_superio(void);
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void mainboard_config_rcba(void);
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