haswell: Drop GPIO indirection layers

This simplifies things and makes type checking possible.

Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This commit is contained in:
Angel Pons 2020-07-03 13:51:15 +02:00
parent f0b5e91b1b
commit 03f0e43a3c
11 changed files with 6 additions and 17 deletions

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@ -72,7 +72,6 @@ void mainboard_romstage_entry(void)
struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
};
romstage_common(&romstage_params);

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@ -72,7 +72,6 @@ void mainboard_romstage_entry(void)
struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
};
romstage_common(&romstage_params);

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@ -11,8 +11,6 @@
#include <superio/ite/it8772f/it8772f.h>
#include "onboard.h"
extern const struct pch_lp_gpio_map mainboard_gpio_map[];
void mainboard_config_rcba(void)
{
/*
@ -107,7 +105,6 @@ void mainboard_romstage_entry(void)
struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
};
/* Early SuperIO setup */

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@ -8,8 +8,6 @@
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include "variant.h"
extern const struct pch_lp_gpio_map mainboard_gpio_map[];
void mainboard_config_rcba(void)
{
/*
@ -77,7 +75,6 @@ void mainboard_romstage_entry(void)
struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
};
variant_romstage_entry(&romstage_params);

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@ -114,7 +114,6 @@ void mainboard_romstage_entry(void)
struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
.copy_spd = NULL,
};

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@ -74,7 +74,6 @@ void mainboard_romstage_entry(void)
struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
};
romstage_common(&romstage_params);

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@ -70,7 +70,6 @@ void mainboard_romstage_entry(void)
struct romstage_params romstage_params = {
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
};
romstage_common(&romstage_params);

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@ -192,7 +192,6 @@ void intel_northbridge_haswell_finalize_smm(void);
struct pei_data;
struct romstage_params {
struct pei_data *pei_data;
const void *gpio_map;
void (*copy_spd)(struct pei_data *peid);
};
void romstage_common(const struct romstage_params *params);

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@ -19,7 +19,7 @@ void romstage_common(const struct romstage_params *params)
enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map);
wake_from_s3 = early_pch_init();
/* Perform some early chipset initialization required
* before RAM initialization can work

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@ -13,6 +13,7 @@
#if CONFIG(INTEL_LYNXPOINT_LP)
#include "lp_gpio.h"
extern const struct pch_lp_gpio_map mainboard_gpio_map[];
#else
#include <southbridge/intel/common/gpio.h>
#endif
@ -77,16 +78,16 @@ void __weak mainboard_config_superio(void)
{
}
int early_pch_init(const void *gpio_map)
int early_pch_init(void)
{
int wake_from_s3;
pch_enable_bars();
#if CONFIG(INTEL_LYNXPOINT_LP)
setup_pch_lp_gpios(gpio_map);
setup_pch_lp_gpios(mainboard_gpio_map);
#else
setup_pch_gpios(gpio_map);
setup_pch_gpios(&mainboard_gpio_map);
#endif
pch_generic_setup();

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@ -121,7 +121,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet);
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void enable_usb_bar(void);
int early_pch_init(const void *gpio_map);
int early_pch_init(void);
void pch_enable_lpc(void);
void mainboard_config_superio(void);
void mainboard_config_rcba(void);