soc/intel/skylake: Enable HDA depending on devicetree configuration

Currently HDA gets enabled by the option EnableAzalia, but
this duplicates the devicetree on/off options. Therefore use
the on/off options for the enablement of the HDA controller.

I checked all corresponding mainboards if the devicetree configuration
matches the EnableAzalia setting.

Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2020-07-25 14:31:58 +02:00 committed by Michael Niewöhner
parent 91dfb92038
commit 048d9b5cba
24 changed files with 6 additions and 24 deletions

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@ -46,7 +46,6 @@ chip soc/intel/skylake
register "SataPortsDevSlp[0]" = "1"
register "SataPortsDevSlp[1]" = "1"
register "SataPortsDevSlp[2]" = "1"
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"

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@ -36,7 +36,6 @@ chip soc/intel/skylake
register "Device4Enable" = "1"
register "SaGv" = "SaGv_Enabled"
register "PmTimerDisabled" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "PchHdaVcType" = "Vc1"

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@ -36,7 +36,6 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
register "EnableAzalia" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"

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@ -39,7 +39,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"

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@ -70,7 +70,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"

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@ -41,7 +41,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"

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@ -45,7 +45,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"

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@ -35,7 +35,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"

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@ -34,7 +34,6 @@ chip soc/intel/skylake
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"

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@ -35,7 +35,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"

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@ -40,7 +40,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"

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@ -45,7 +45,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"

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@ -35,7 +35,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"

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@ -157,7 +157,7 @@ chip soc/intel/skylake
device pci 1f.0 on end # LPC Interface
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA
device pci 1f.3 off end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE

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@ -1,7 +1,6 @@
chip soc/intel/skylake
# FSP Configuration
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "ScsEmmcHs400Enabled" = "0"
@ -126,6 +125,7 @@ chip soc/intel/skylake
device pci 1e.3 on end # GSPI #1
device pci 1e.4 off end # eMMC
device pci 1e.6 off end # SDCard
device pci 1f.3 on end # Intel HDA
device pci 1f.6 on end # GbE
end
end

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@ -7,7 +7,6 @@ chip soc/intel/skylake
register "gen2_dec" = "0x000c0201"
# FSP Configuration
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "0"
register "HeciEnabled" = "0"
@ -134,5 +133,6 @@ chip soc/intel/skylake
device pnp 0c31.0 on end
end
end # LPC Interface
device pci 1f.3 on end # Intel HDA
end
end

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@ -24,7 +24,6 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"

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@ -18,7 +18,6 @@ chip soc/intel/skylake
register "speed_shift_enable" = "1"
# FSP Configuration
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "0"

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@ -47,7 +47,6 @@ chip soc/intel/skylake
register "SataPortsDevSlp[1]" = "0"
register "SataPortsDevSlp[2]" = "0"
register "SataSpeedLimit" = "2"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"

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@ -36,7 +36,6 @@ chip soc/intel/skylake
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "EnableAzalia" = "0"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"

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@ -52,7 +52,6 @@ chip soc/intel/skylake
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[2]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"

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@ -32,7 +32,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "SataPortsEnable[1]" = "0"
register "SataPortsEnable[2]" = "0"
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"

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@ -272,7 +272,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev = pcidev_path_on_root(PCH_DEVFN_ISH);
params->PchIshEnable = dev ? dev->enabled : 0;
params->PchHdaEnable = config->EnableAzalia;
dev = pcidev_path_on_root(PCH_DEVFN_HDA);
params->PchHdaEnable = dev ? dev->enabled : 0;
params->PchHdaVcType = config->PchHdaVcType;
params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
params->PchHdaDspEnable = config->DspEnable;

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@ -157,7 +157,6 @@ struct soc_intel_skylake_config {
u8 SataSpeedLimit;
/* Audio related */
u8 EnableAzalia;
u8 DspEnable;
/* HDA Virtual Channel Type Select */