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soc/intel/skylake: Enable HECI3 depending on devicetree configuration 

Currently HECI3 gets enabled by the option Heci3Enabled, but
this duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the HECI3 controller.

I checked all corresponding mainboards if the devicetree configuration
matches the Heci3Enabled setting.

Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2020-07-25 14:01:52 +02:00 committed by Michael Niewöhner
parent aff69be254
commit 91dfb92038
4 changed files with 3 additions and 4 deletions
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1
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
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@ -7,7 +7,6 @@ chip soc/intel/skylake
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "Device4Enable" = "0"
register "Heci3Enabled" = "0"
register "PmTimerDisabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS"

1
src/mainboard/intel/saddlebrook/devicetree.cb
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@ -25,7 +25,6 @@ chip soc/intel/skylake
register "ScsSdCardEnabled" = "0"
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "0"
register "Heci3Enabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmTimerDisabled" = "0"

4
src/soc/intel/skylake/chip.c
View File

@ -231,7 +231,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchCio2Enable = config->Cio2Enable;
params->SaImguEnable = config->SaImguEnable;
params->Heci3Enabled = config->Heci3Enabled;
dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
params->Heci3Enabled = dev ? dev->enabled : 0;
params->LogoPtr = config->LogoPtr;
params->LogoSize = config->LogoSize;

1
src/soc/intel/skylake/chip.h
View File

@ -315,7 +315,6 @@ struct soc_intel_skylake_config {
u8 PttSwitch;
u8 HeciTimeouts;
u8 HsioMessaging;
u8 Heci3Enabled;
/* Gfx related */
u8 IgdDvmt50PreAlloc;