soc/intel/common/block: Add HECI driver
Add common driver that can send/receive HECI messages. This driver is inspired by Linux kernel mei driver and somewhat based on Skylake's. Currently it has been only tested on Apollolake. BUG=b:35586975 BRANCH=reef TEST=tested on Apollolake to send single messages and receive both fragmented and non-fragmented versions. Change-Id: Ie3772700270f4f333292b80d59f79555851780f7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
This commit is contained in:
Andrey Petrov
Martin Roth
parent
fba7489574
commit
04a72c4019
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@ -0,0 +1,7 @@
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config SOC_INTEL_COMMON_BLOCK_CSE
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bool
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default n
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help
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Driver for communication with Converged Security Engine (CSE)
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over Host Embedded Controller Interface (HECI)
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@ -0,0 +1,2 @@
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romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
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@ -0,0 +1,477 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Intel Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/early_variables.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <intelblocks/cse.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_ids.h>
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#include <string.h>
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#include <timer.h>
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/* default window for early boot, must be at least 12 bytes in size */
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#define HECI1_BASE_ADDRESS 0xfed1a000
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/* Wait up to 15 sec for HECI to get ready */
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#define HECI_DELAY_READY (15 * 1000)
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/* Wait up to 100 usec between circullar buffer polls */
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#define HECI_DELAY 100
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/* Wait up to 5 sec for CSE to chew something we sent */
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#define HECI_SEND_TIMEOUT (5 * 1000)
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/* Wait up to 5 sec for CSE to blurp a reply */
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#define HECI_READ_TIMEOUT (5 * 1000)
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#define SLOT_SIZE sizeof(uint32_t)
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#define MMIO_CSE_CB_WW 0x00
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#define MMIO_HOST_CSR 0x04
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#define MMIO_CSE_CB_RW 0x08
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#define MMIO_CSE_CSR 0x0c
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#define CSR_IE (1 << 0)
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#define CSR_IS (1 << 1)
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#define CSR_IG (1 << 2)
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#define CSR_READY (1 << 3)
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#define CSR_RESET (1 << 4)
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#define CSR_RP_START 8
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#define CSR_RP (((1 << 8) - 1) << CSR_RP_START)
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#define CSR_WP_START 16
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#define CSR_WP (((1 << 8) - 1) << CSR_WP_START)
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#define CSR_CBD_START 24
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#define CSR_CBD (((1 << 8) - 1) << CSR_CBD_START)
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#define MEI_HDR_IS_COMPLETE (1 << 31)
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#define MEI_HDR_LENGTH_START 16
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#define MEI_HDR_LENGTH_SIZE 9
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#define MEI_HDR_LENGTH (((1 << MEI_HDR_LENGTH_SIZE) - 1) \
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<< MEI_HDR_LENGTH_START)
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#define MEI_HDR_HOST_ADDR_START 8
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#define MEI_HDR_HOST_ADDR (((1 << 8) - 1) << MEI_HDR_HOST_ADDR_START)
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#define MEI_HDR_CSE_ADDR_START 0
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#define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START)
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struct cse_device {
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uintptr_t sec_bar;
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} g_cse CAR_GLOBAL;
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/*
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* Initialize the device with provided temporary BAR. If BAR is 0 use a
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* default. This is intended for pre-mem usage only where BARs haven't been
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* assigned yet and devices are not enabled.
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*/
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void heci_init(uintptr_t tempbar)
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{
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struct cse_device *cse = car_get_var_ptr(&g_cse);
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device_t dev = HECI1_DEV;
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u8 pcireg;
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/* Assume it is already initialized, nothing else to do */
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if (cse->sec_bar)
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return;
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/* Use default pre-ram bar */
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if (!tempbar)
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tempbar = HECI1_BASE_ADDRESS;
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/* Assign Resources to HECI1 */
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/* Clear BIT 1-2 of Command Register */
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pcireg = pci_read_config8(dev, PCI_COMMAND);
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pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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pci_write_config8(dev, PCI_COMMAND, pcireg);
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/* Program Temporary BAR for HECI1 */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar);
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pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0);
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/* Enable Bus Master and MMIO Space */
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pcireg = pci_read_config8(dev, PCI_COMMAND);
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pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config8(dev, PCI_COMMAND, pcireg);
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cse->sec_bar = tempbar;
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}
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static uint32_t read_bar(uint32_t offset)
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{
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struct cse_device *cse = car_get_var_ptr(&g_cse);
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return read32((void *)(cse->sec_bar + offset));
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}
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static void write_bar(uint32_t offset, uint32_t val)
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{
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struct cse_device *cse = car_get_var_ptr(&g_cse);
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return write32((void *)(cse->sec_bar + offset), val);
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}
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static uint32_t read_cse_csr(void)
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{
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return read_bar(MMIO_CSE_CSR);
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}
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static uint32_t read_host_csr(void)
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{
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return read_bar(MMIO_HOST_CSR);
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}
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static void write_host_csr(uint32_t data)
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{
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write_bar(MMIO_HOST_CSR, data);
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}
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static size_t filled_slots(uint32_t data)
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{
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uint8_t wp, rp;
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rp = data >> CSR_RP_START;
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wp = data >> CSR_WP_START;
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return (uint8_t) (wp - rp);
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}
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static size_t cse_filled_slots(void)
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{
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return filled_slots(read_cse_csr());
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}
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static size_t host_empty_slots(void)
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{
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uint32_t csr;
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csr = read_host_csr();
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return ((csr & CSR_CBD) >> CSR_CBD_START) - filled_slots(csr);
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}
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static void clear_int(void)
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{
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uint32_t csr;
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csr = read_host_csr();
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csr |= CSR_IS;
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write_host_csr(csr);
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}
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static uint32_t read_slot(void)
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{
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return read_bar(MMIO_CSE_CB_RW);
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}
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static void write_slot(uint32_t val)
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{
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write_bar(MMIO_CSE_CB_WW, val);
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}
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static int wait_write_slots(size_t cnt)
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{
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struct stopwatch sw;
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stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT);
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while (host_empty_slots() < cnt) {
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udelay(HECI_DELAY);
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR, "HECI: timeout, buffer not drained\n");
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return 0;
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}
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}
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return 1;
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}
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static int wait_read_slots(size_t cnt)
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{
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struct stopwatch sw;
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stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT);
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while (cse_filled_slots() < cnt) {
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udelay(HECI_DELAY);
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR, "HECI: timed out reading answer!\n");
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return 0;
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}
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}
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return 1;
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}
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/* get number of full 4-byte slots */
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static size_t bytes_to_slots(size_t bytes)
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{
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return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE;
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}
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static int cse_ready(void)
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{
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uint32_t csr;
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csr = read_cse_csr();
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return csr & CSR_READY;
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}
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static int wait_heci_ready(void)
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{
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struct stopwatch sw;
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stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY);
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while (!cse_ready()) {
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udelay(HECI_DELAY);
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if (stopwatch_expired(&sw))
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return 0;
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}
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return 1;
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}
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static void host_gen_interrupt(void)
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{
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uint32_t csr;
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csr = read_host_csr();
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csr |= CSR_IG;
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write_host_csr(csr);
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}
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static size_t hdr_get_length(uint32_t hdr)
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{
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return (hdr & MEI_HDR_LENGTH) >> MEI_HDR_LENGTH_START;
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}
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static int
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send_one_message(uint32_t hdr, const void *buff)
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{
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size_t pend_len, pend_slots, remainder, i;
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uint32_t tmp;
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const uint32_t *p = buff;
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/* Get space for the header */
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if (!wait_write_slots(1))
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return 0;
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/* First, write header */
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write_slot(hdr);
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pend_len = hdr_get_length(hdr);
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pend_slots = bytes_to_slots(pend_len);
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if (!wait_write_slots(pend_slots))
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return 0;
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/* Write the body in whole slots */
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i = 0;
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while (i < ALIGN_DOWN(pend_len, SLOT_SIZE)) {
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write_slot(*p++);
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i += SLOT_SIZE;
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}
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remainder = pend_len % SLOT_SIZE;
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/* Pad to 4 bytes not touching caller's buffer */
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if (remainder) {
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memcpy(&tmp, p, remainder);
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write_slot(tmp);
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}
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host_gen_interrupt();
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/* Make sure nothing bad happened during transmission */
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if (!cse_ready())
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return 0;
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return pend_len;
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}
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int
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heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr)
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{
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uint32_t csr, hdr;
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size_t sent = 0, remaining, cb_size, max_length;
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uint8_t *p = (uint8_t *) msg;
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if (!msg || !len)
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return 0;
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clear_int();
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if (!wait_heci_ready()) {
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printk(BIOS_ERR, "HECI: not ready\n");
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return 0;
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}
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csr = read_cse_csr();
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cb_size = ((csr & CSR_CBD) >> CSR_CBD_START) * SLOT_SIZE;
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/*
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* Reserve one slot for the header. Limit max message length by 9
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* bits that are available in the header.
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*/
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max_length = MIN(cb_size, (1 << MEI_HDR_LENGTH_SIZE) - 1) - SLOT_SIZE;
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remaining = len;
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/*
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* Fragment the message into smaller messages not exceeding useful
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* circullar buffer length. Mark last message complete.
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*/
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do {
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hdr = MIN(max_length, remaining) << MEI_HDR_LENGTH_START;
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hdr |= client_addr << MEI_HDR_CSE_ADDR_START;
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hdr |= host_addr << MEI_HDR_HOST_ADDR_START;
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hdr |= (MIN(max_length, remaining) == remaining) ?
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MEI_HDR_IS_COMPLETE: 0;
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sent = send_one_message(hdr, p);
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p += sent;
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remaining -= sent;
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} while (remaining > 0 && sent != 0);
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return remaining == 0;
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}
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static size_t
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recv_one_message(uint32_t *hdr, void *buff, size_t maxlen)
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{
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uint32_t reg, *p = buff;
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size_t recv_slots, recv_len, remainder, i;
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/* first get the header */
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if (!wait_read_slots(1))
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return 0;
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*hdr = read_slot();
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recv_len = hdr_get_length(*hdr);
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if (!recv_len)
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printk(BIOS_WARNING, "HECI: message is zero-sized\n");
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recv_slots = bytes_to_slots(recv_len);
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i = 0;
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if (recv_len > maxlen) {
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printk(BIOS_ERR, "HECI: response is too big\n");
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return 0;
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}
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/* wait for the rest of messages to arrive */
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wait_read_slots(recv_slots);
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/* fetch whole slots first */
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while (i < ALIGN_DOWN(recv_len, SLOT_SIZE)) {
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*p++ = read_slot();
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i += SLOT_SIZE;
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}
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remainder = recv_len % SLOT_SIZE;
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if (remainder) {
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reg = read_slot();
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memcpy(p, ®, remainder);
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}
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return recv_len;
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}
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int heci_receive(void *buff, size_t *maxlen)
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{
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size_t left, received;
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uint32_t hdr = 0;
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uint8_t *p = buff;
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if (!buff || !maxlen || !*maxlen)
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return 0;
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left = *maxlen;
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clear_int();
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if (!wait_heci_ready()) {
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printk(BIOS_ERR, "HECI: not ready\n");
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return 0;
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}
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/*
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* Receive multiple packets until we meet one marked complete or we run
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* out of space in caller-provided buffer.
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*/
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do {
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received = recv_one_message(&hdr, p, left);
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left -= received;
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p += received;
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/* If we read out everything ping to send more */
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if (!(hdr & MEI_HDR_IS_COMPLETE) && !cse_filled_slots())
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host_gen_interrupt();
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} while (received && !(hdr & MEI_HDR_IS_COMPLETE) && left > 0);
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*maxlen = p - (uint8_t *) buff;
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/* If ME is not ready, something went wrong and we received junk */
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if (!cse_ready())
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return 0;
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return !!((hdr & MEI_HDR_IS_COMPLETE) && received);
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}
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/*
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* Attempt to reset the device. This is useful when host and ME are out
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* of sync during transmission or ME didn't understand the message.
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*/
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int heci_reset(void)
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{
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uint32_t csr;
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/* Send reset request */
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csr = read_host_csr();
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csr |= CSR_RESET;
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csr |= CSR_IG;
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write_host_csr(csr);
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if (wait_heci_ready()) {
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/* Device is back on its imaginary feet, clear reset */
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csr = read_host_csr();
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csr &= ~CSR_RESET;
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csr |= CSR_IG;
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csr |= CSR_READY;
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write_host_csr(csr);
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return 1;
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}
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printk(BIOS_CRIT, "HECI: reset failed\n");
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return 0;
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}
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#if ENV_RAMSTAGE
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static void update_sec_bar(struct device *dev)
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{
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g_cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base;
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}
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static void cse_set_resources(struct device *dev)
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{
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if (dev->path.pci.devfn == HECI1_DEVFN)
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update_sec_bar(dev);
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pci_dev_set_resources(dev);
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}
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static struct device_operations cse_ops = {
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.set_resources = cse_set_resources,
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.read_resources = pci_dev_read_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = pci_dev_init,
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.enable_resources = pci_dev_enable_resources
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};
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static const struct pci_driver cse_driver __pci_driver = {
|
||||
.ops = &cse_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
/* SoC/chipset needs to provide PCI device ID */
|
||||
.device = PCI_DEVICE_ID_HECI1
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef SOC_INTEL_COMMON_CSE_H
|
||||
#define SOC_INTEL_COMMON_CSE_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* set up device for use in early boot enviroument with temp bar */
|
||||
void heci_init(uintptr_t bar);
|
||||
/*
|
||||
* Receive message into buff not exceeding maxlen. Message is considered
|
||||
* successfully received if a 'complete' indication is read from ME side
|
||||
* and there was enough space in the buffer to fit that message. maxlen
|
||||
* is updated with size of message that was received. Returns 0 on failure
|
||||
* and 1 on success.
|
||||
* In case of error heci_reset() may be requiered.
|
||||
*/
|
||||
int heci_receive(void *buff, size_t *maxlen);
|
||||
/*
|
||||
* Send message msg of size len to host from host_addr to cse_addr.
|
||||
* Returns 1 on success and 0 otherwise.
|
||||
* In case of error heci_reset() may be requiered.
|
||||
*/
|
||||
int
|
||||
heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t cse_addr);
|
||||
/*
|
||||
* Attempt device reset. This is useful and perhaps only thing left to do when
|
||||
* CPU and CSE are out of sync or CSE fails to respond.
|
||||
* Returns 0 on failure a 1 on success.
|
||||
*/
|
||||
int heci_reset(void);
|
||||
|
||||
#define BIOS_HOST_ADDR 0x00
|
||||
#define HECI_MKHI_ADDR 0x07
|
||||
|
||||
#endif // SOC_INTEL_COMMON_MSR_H
|
||||
Loading…
Reference in New Issue