GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

amdfam10: Declare get_sysinfo() 

It's forbidden to use dereference CAR_GLOBAL variables
directly. The notation fails after CAR teardown for
romstage.

Change-Id: I6e6285ca0f520608c2a344517fbac943aeb36d87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33995
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-07-03 06:50:19 +03:00
parent 8560db6116
commit 04d025cf50
26 changed files with 31 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/advansus/a785e-i/romstage.c
View File

@ -46,7 +46,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -56,7 +55,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/amd/bimini_fam10/romstage.c
View File

@ -42,7 +42,6 @@
#include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/quadcore/quadcore.c"
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -52,7 +51,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -46,7 +46,6 @@
#include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/quadcore/quadcore.c"
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -42,7 +42,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
static void memreset_setup(void) static void memreset_setup(void)
{ {
@ -167,7 +166,7 @@ static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -44,7 +44,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -55,7 +54,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/asus/kcma-d8/romstage.c
View File

@ -51,7 +51,6 @@
#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
inline int spd_read_byte(unsigned int device, unsigned int address) inline int spd_read_byte(unsigned int device, unsigned int address)
{ {
@ -355,7 +354,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
: "=r" (esp) : "=r" (esp)
); );
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
/* Limit the maximum HT speed to 2.6GHz to prevent lockups /* Limit the maximum HT speed to 2.6GHz to prevent lockups
* due to HT CPU <--> CPU wiring not being validated to 3.2GHz * due to HT CPU <--> CPU wiring not being validated to 3.2GHz

3
src/mainboard/asus/kfsn4-dre/romstage.c
View File

@ -54,7 +54,6 @@
#define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(unsigned int device, unsigned int address) int spd_read_byte(unsigned int device, unsigned int address)
{ {
@ -184,7 +183,7 @@ void activate_spd_rom(const struct mem_controller *ctrl)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
u32 bsp_apicid = 0, val, wants_reset; u32 bsp_apicid = 0, val, wants_reset;
msr_t msr; msr_t msr;

5
src/mainboard/asus/kgpe-d16/romstage.c
View File

@ -52,7 +52,6 @@
#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2) #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(unsigned int device, unsigned int address) int spd_read_byte(unsigned int device, unsigned int address)
{ {
@ -180,7 +179,7 @@ static const uint8_t spd_addr_fam10[] = {
void activate_spd_rom(const struct mem_controller *ctrl) void activate_spd_rom(const struct mem_controller *ctrl)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
if (ctrl->node_id == 0) { if (ctrl->node_id == 0) {
printk(BIOS_DEBUG, "enable_spd_node0()\n"); printk(BIOS_DEBUG, "enable_spd_node0()\n");
@ -467,7 +466,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
: "=r" (esp) : "=r" (esp)
); );
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
/* Limit the maximum HT speed to 2.6GHz to prevent lockups /* Limit the maximum HT speed to 2.6GHz to prevent lockups
* due to HT CPU <--> CPU wiring not being validated to 3.2GHz * due to HT CPU <--> CPU wiring not being validated to 3.2GHz

3
src/mainboard/asus/m4a78-em/romstage.c
View File

@ -47,7 +47,6 @@
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -47,7 +47,6 @@
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/asus/m5a88-v/romstage.c
View File

@ -47,7 +47,6 @@
#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -58,7 +57,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/avalue/eax-785e/romstage.c
View File

@ -46,7 +46,6 @@
#define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1) #define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -56,7 +55,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/gigabyte/ma785gm/romstage.c
View File

@ -47,7 +47,6 @@
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@ -47,7 +47,6 @@
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@ -47,7 +47,6 @@
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -57,7 +56,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/hp/dl165_g6_fam10/romstage.c
View File

@ -53,7 +53,6 @@
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
void activate_spd_rom(const struct mem_controller *ctrl) void activate_spd_rom(const struct mem_controller *ctrl)
{ {
@ -83,7 +82,7 @@ static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -46,7 +46,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -56,7 +55,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -51,7 +51,6 @@
#endif #endif
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -61,7 +60,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0, val; u32 bsp_apicid = 0, val;
msr_t msr; msr_t msr;

3
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -45,7 +45,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
inline int spd_read_byte(unsigned int device, unsigned int address) inline int spd_read_byte(unsigned int device, unsigned int address)
@ -100,7 +99,7 @@ static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
u32 bsp_apicid = 0, val, wants_reset; u32 bsp_apicid = 0, val, wants_reset;
u8 reg; u8 reg;
msr_t msr; msr_t msr;

3
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -48,7 +48,6 @@
#define SUPERIO_DEV PNP_DEV(0x2e, 0) #define SUPERIO_DEV PNP_DEV(0x2e, 0)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
inline int spd_read_byte(unsigned int device, unsigned int address) inline int spd_read_byte(unsigned int device, unsigned int address)
@ -101,7 +100,7 @@ static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
u32 bsp_apicid = 0, val, wants_reset; u32 bsp_apicid = 0, val, wants_reset;
msr_t msr; msr_t msr;

3
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -51,7 +51,6 @@
#define SMBUS_SWITCH2 0x72 #define SMBUS_SWITCH2 0x72
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
void activate_spd_rom(const struct mem_controller *ctrl) void activate_spd_rom(const struct mem_controller *ctrl)
{ {
@ -154,7 +153,7 @@ static void write_GPIO(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
u32 bsp_apicid = 0, val, wants_reset; u32 bsp_apicid = 0, val, wants_reset;
msr_t msr; msr_t msr;

3
src/mainboard/supermicro/h8scm_fam10/romstage.c
View File

@ -43,7 +43,6 @@
#include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/quadcore/quadcore.c"
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address) int spd_read_byte(u32 device, u32 address)
@ -53,7 +52,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = { static const u8 spd_addr[] = {
RC00, 0x52, 0x53, 0, 0, 0x50, 0x51, 0, 0, RC00, 0x52, 0x53, 0, 0, 0x50, 0x51, 0, 0,
//RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0, //RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0,

3
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -44,7 +44,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
int spd_read_byte(unsigned int device, unsigned int address); int spd_read_byte(unsigned int device, unsigned int address);
extern struct sys_info sysinfo_car;
inline int spd_read_byte(unsigned int device, unsigned int address) inline int spd_read_byte(unsigned int device, unsigned int address)
@ -104,7 +103,7 @@ static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = &sysinfo_car; struct sys_info *sysinfo = get_sysinfo();
u32 bsp_apicid = 0, val, wants_reset; u32 bsp_apicid = 0, val, wants_reset;
msr_t msr; msr_t msr;

6
src/northbridge/amd/amdfam10/amdfam10.h
View File

@ -989,12 +989,6 @@ struct sys_info {
struct DCTStatStruc DCTstatA[NODE_NUMS]; struct DCTStatStruc DCTstatA[NODE_NUMS];
} __packed; } __packed;
/*
#ifdef __PRE_RAM__
extern struct sys_info sysinfo_car;
#endif
*/
#ifndef __PRE_RAM__ #ifndef __PRE_RAM__
struct device *get_node_pci(u32 nodeid, u32 fn); struct device *get_node_pci(u32 nodeid, u32 fn);
#endif #endif

1
src/northbridge/amd/amdfam10/raminit.h
View File

@ -30,6 +30,7 @@ int mctRead_SPD(u32 smaddr, u32 reg);
void mctSMBhub_Init(u32 node); void mctSMBhub_Init(u32 node);
void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node); void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node);
void set_sysinfo_in_ram(u32 val); void set_sysinfo_in_ram(u32 val);
struct sys_info *get_sysinfo(void);
void raminit_amdmct(struct sys_info *sysinfo); void raminit_amdmct(struct sys_info *sysinfo);
void amdmct_cbmem_store_info(struct sys_info *sysinfo); void amdmct_cbmem_store_info(struct sys_info *sysinfo);
void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr); void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr);

7
src/northbridge/amd/amdfam10/raminit_amdmct.c
View File

@ -29,7 +29,12 @@
/* Global allocation of sysinfo_car */ /* Global allocation of sysinfo_car */
#include <arch/early_variables.h> #include <arch/early_variables.h>
struct sys_info sysinfo_car CAR_GLOBAL; static struct sys_info sysinfo_car CAR_GLOBAL;
struct sys_info *get_sysinfo(void)
{
return car_get_var_ptr(&sysinfo_car);
}
struct mem_controller; struct mem_controller;
extern int spd_read_byte(unsigned int device, unsigned int address); extern int spd_read_byte(unsigned int device, unsigned int address);