This patch adds high table support to qemu. It was already added to
src/northbridge/intel/i440bx/ but not to src/cpu/emulation/qemu-x86/northbridge.c It also adds a driver for the ISA device that is found when using 0.9.1 If you look in a log without this patch you won't find the RTC init lines. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -65,6 +65,11 @@ static uint32_t find_pci_tolm(struct bus *bus)
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return tolm;
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}
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#if HAVE_HIGH_TABLES==1
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#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
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extern uint64_t high_tables_base, high_tables_size;
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#endif
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static void pci_domain_set_resources(device_t dev)
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{
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static const uint8_t ramregs[] = {
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@ -110,7 +115,14 @@ static void pci_domain_set_resources(device_t dev)
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/* Report the memory regions. */
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idx = 10;
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ram_resource(dev, idx++, 0, tolmk);
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 768, tolmk - 768);
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#if HAVE_HIGH_TABLES==1
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/* Leave some space for ACPI, PIRQ and MP tables */
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high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
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high_tables_size = HIGH_TABLES_SIZE * 1024;
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#endif
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}
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assign_resources(&dev->link[0]);
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}
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@ -31,6 +31,7 @@ uses _RAMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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uses HAVE_HIGH_TABLES
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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@ -80,6 +81,8 @@ default HAVE_HARD_RESET=0
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=6
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default HAVE_HIGH_TABLES=1
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##
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## Build code to export a CMOS option table
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##
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@ -70,3 +70,9 @@ static const struct pci_driver isa_driver __pci_driver = {
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82371AB_ISA,
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};
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static const struct pci_driver isa_SB_driver __pci_driver = {
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.ops = &isa_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82371SB_ISA,
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};
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