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soc/intel/xeon_sp/cpx: remove unsupported configs 

coherency_support and ats_support are not supported by CPX-SP FSP.

Remove them from soc_intel_xeon_sp_cpx_config struct.

Remove corresponding settings from DeltaLake devicetree.cb.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ibe1c4e88817fc4be7915e95fa829f0a4c0d947f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This commit is contained in:
Jonathan Zhang 2020-08-11 16:27:42 -07:00 committed by Angel Pons
parent 6e36ee2544
commit 056f81988f
2 changed files with 0 additions and 6 deletions
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3
src/mainboard/ocp/deltalake/devicetree.cb
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@ -33,9 +33,6 @@ chip soc/intel/xeon_sp/cpx
# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
register "pstate_req_ratio" = "0xa"
register "coherency_support" = "0"
register "ats_support" = "0"
register "gen1_dec" = "0x00fc0601" # BIC in-band update support
register "gen2_dec" = "0x000c0ca1" # IPMI KCS

3
src/soc/intel/xeon_sp/cpx/chip.h
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@ -84,9 +84,6 @@ struct soc_intel_xeon_sp_cpx_config {
uint32_t pstate_req_ratio;
uint32_t coherency_support;
uint32_t ats_support;
/* Generic IO decode ranges */
uint32_t gen1_dec;
uint32_t gen2_dec;