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soc/intel/tigerlake: Set TME upd param based on config 

Set TmeEnable FSP-M upd based on config.

TEST: TME ENABLE and LOCK bits get set when Tme is enabled.

Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Ia804c88057e17844f055fd852fc0b36cfe316432
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Pratik Prajapati 2020-09-17 11:49:11 -07:00 committed by Patrick Georgi
parent 3554888f25
commit 05ea79cf53
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/tigerlake/romstage/fsp_params.c
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@ -211,6 +211,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;
/* Change TmeEnable UPD value according to INTEL_TME Kconfig */
m_cfg->TmeEnable = CONFIG(INTEL_TME);
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)