soc/amd/stoneyridge: utilize full SPI flash controller fifo
The spi flash host controller has a dedicated register for the opcode. Therefore, indicate to the spi subsystem that the opcode size should not be taken into account when determining maximum payload size in spi_crop_chunk(). This allows the full use of the fifo when doing transfers. BUG=b:65485690 Change-Id: Iab27a69ca72fd02bc443f0673983f3b22ffca0f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23492 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
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@ -193,7 +193,7 @@ static const struct spi_ctrlr spi_ctrlr = {
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.xfer = spi_ctrlr_xfer,
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.xfer_vector = spi_xfer_two_vectors,
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.max_xfer_size = SPI_FIFO_DEPTH,
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.flags = SPI_CNTRLR_DEDUCT_CMD_LEN,
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.flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN,
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};
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const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
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