soc/mediatek/mt8192: Refactor USB code among similar SoCs

Adjust ssusb register layout and offset accroding mt8192 Soc
then refactor USB code which will be reused among similar SoCs

Signed-off-by: Tianping Fang <tianping.fang@mediatek.com>
Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
Change-Id: Icb4cc304654b5fb7cf20b96ab83a22663bfeab63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

src/soc/mediatek/mt8192/Makefile.inc

@@ -32,6 +32,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += soc.c
 ramstage-y += ../common/timer.c
 ramstage-y += ../common/uart.c
+ramstage-y += ../common/usb.c usb.c
 
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include
 CPPFLAGS_common += -Isrc/soc/mediatek/common/include

src/soc/mediatek/mt8192/include/soc/usb.h

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8192_USB_H
+#define SOC_MEDIATEK_MT8192_USB_H
+
+#include <soc/usb_common.h>
+
+struct ssusb_sif_port {
+	struct sif_u2_phy_com u2phy;
+	u32 reserved0[64*5];
+	struct sif_u3phyd u3phyd;
+	u32 reserved1[64];
+	struct sif_u3phya u3phya;
+	struct sif_u3phya_da u3phya_da;
+	u32 reserved2[64 * 3];
+};
+check_member(ssusb_sif_port, u3phyd, 0x600);
+check_member(ssusb_sif_port, u3phya, 0x800);
+check_member(ssusb_sif_port, u3phya_da, 0x900);
+check_member(ssusb_sif_port, reserved2, 0xa00);
+
+#define USB_PORT_NUMBER 2
+
+#endif

src/soc/mediatek/mt8192/usb.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/addressmap.h>
+#include <device/mmio.h>
+#include <soc/usb.h>
+
+#define REG_SPM_POWERON_CONFIG_EN          (void *)(SPM_BASE + 0x000)
+#define REG_SPM_SSPM_PWR_CON               (void *)(SPM_BASE + 0x390)
+
+void mtk_usb_prepare(void)
+{
+	/* power on SSUSB SRAM FIFO */
+	setbits32(REG_SPM_POWERON_CONFIG_EN, 0xB160001);
+	clrbits32(REG_SPM_SSPM_PWR_CON, 0x000001FF);
+}