GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/intel/tglrvp: Enable rp11 for optane 

Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage
device and NVMe Optane memory. Storage device uses rp9 and optane memory
uses rp11. This patch enables rp11. Please note that these two share clk pins.

This is also dependent on pciecontroller3 config to be set as 2x2 instead of
1x4 in fit configuration in IFWI.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board from Optane and check 2 NVMe devices
from lspci

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ic81244bebac78102af7ba6308ab64b18c886f839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Wonkyu Kim 2020-01-22 23:48:52 -08:00 committed by Patrick Georgi
parent 591b0ff535
commit 06e067e4cf
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -35,7 +35,7 @@ chip soc/intel/tigerlake
register "PcieRpEnable[2]" = "1" register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1" register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[8]" = "1" register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[9]" = "1" register "PcieRpEnable[10]" = "1"
register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[2]" = "2"
@ -139,8 +139,8 @@ chip soc/intel/tigerlake
device pci 1c.6 off end # RP7 0xA0BE device pci 1c.6 off end # RP7 0xA0BE
device pci 1c.7 off end # RP8 0xA0BF device pci 1c.7 off end # RP8 0xA0BF
device pci 1d.0 on end # RP9 0xA0B0 device pci 1d.0 on end # RP9 0xA0B0
device pci 1d.1 on end # RP10 0xA0B1 device pci 1d.1 off end # RP10 0xA0B1
device pci 1d.2 off end # RP11 0xA0B2 device pci 1d.2 on end # RP11 0xA0B2
device pci 1d.3 off end # RP12 0xA0B3 device pci 1d.3 off end # RP12 0xA0B3
device pci 1e.0 off end # UART0 0xA0A8 device pci 1e.0 off end # UART0 0xA0A8
device pci 1e.1 off end # UART1 0xA0A9 device pci 1e.1 off end # UART1 0xA0A9