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soc/amd/common: Add AcpiMmio access for SMBus PCI device 

The standard PCI register space for D14F0 is accessible at 0xfed80000.
Add functions for use as helpers.

Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2019-08-16 12:46:45 -06:00 committed by Martin Roth
parent f6dbf4a46a
commit 06fd982030
2 changed files with 44 additions and 1 deletions
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34
src/soc/amd/common/block/acpimmio/mmio_util.c
View File

@ -65,7 +65,39 @@ void pm_io_write32(uint8_t reg, uint32_t value)
pm_io_write16(reg + sizeof(uint16_t), value & 0xffff);
}
/* smbus pci read/write - access registers at 0xfed80000 - currently unused */
#if SUPPORTS_ACPIMMIO_SM_PCI_BASE
/* smbus pci read/write - access registers at 0xfed80000 */
u8 sm_pci_read8(u8 reg)
{
return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg));
}
u16 sm_pci_read16(u8 reg)
{
return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg));
}
u32 sm_pci_read32(u8 reg)
{
return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg));
}
void sm_pci_write8(u8 reg, u8 value)
{
write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value);
}
void sm_pci_write16(u8 reg, u16 value)
{
write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value);
}
void sm_pci_write32(u8 reg, u32 value)
{
write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value);
}
#endif
#if SUPPORTS_ACPIMMIO_SMI_BASE
/* smi read/write - access registers at 0xfed80200 */

11
src/soc/amd/common/block/include/amdblocks/acpimmio.h
View File

@ -21,6 +21,9 @@
#include <stdint.h>
/* iomap.h must indicate if the device uses a block, optional if unused. */
#include <soc/iomap.h>
#ifndef SUPPORTS_ACPIMMIO_SM_PCI_BASE
#define SUPPORTS_ACPIMMIO_SM_PCI_BASE 0
#endif
#ifndef SUPPORTS_ACPIMMIO_SMI_BASE
#define SUPPORTS_ACPIMMIO_SMI_BASE 0
#endif
@ -162,6 +165,14 @@
/* Enable the AcpiMmio range at 0xfed80000 */
void enable_acpimmio_decode(void);
/* Access SMBus PCI registers at 0xfed80000 */
uint8_t sm_pci_read8(uint8_t reg);
uint16_t sm_pci_read16(uint8_t reg);
uint32_t sm_pci_read32(uint8_t reg);
void sm_pci_write8(uint8_t reg, uint8_t value);
void sm_pci_write16(uint8_t reg, uint16_t value);
void sm_pci_write32(uint8_t reg, uint32_t value);
/* Access PM registers using IO cycles */
uint8_t pm_io_read8(uint8_t reg);
uint16_t pm_io_read16(uint8_t reg);