mainboard/google/poppy/variants/atlas: config ISH in mainboard side
To enable ISH device on atlas board, change "device pci 13.0 off end" to "device pci 13.0 on end" in file mainboard/google/poppy/variants/atlas/devicetree.cb. "IshEnable" is not needed. Config atlas board specific ISH setting in devicetree.cb. Dynamically load gpio setting for ISH enabled/disabled cases. BUG=b:79244403 BRANCH=none TEST=Verified on Atlas board with ISH rework. ISH log showed on console. Change-Id: I8269a85cd2ab7917bfc0e7d63d988e0e678d0bf2 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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2 changed files with 50 additions and 9 deletions
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@ -45,7 +45,6 @@ chip soc/intel/skylake
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "0"
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register "IshEnable" = "0" # FIXME: enable once ISH is ready
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register "PttSwitch" = "0"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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@ -255,6 +254,7 @@ chip soc/intel/skylake
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on end # USB xHCI
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device pci 14.1 on end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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@ -16,6 +16,8 @@
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <device/device.h>
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#include <soc/pci_devs.h>
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/* Pad configuration in ramstage */
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/* Leave eSPI pins untouched from default settings */
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@ -51,10 +53,6 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NC(GPP_A17),
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/* A18 : ISH_GP0 ==> ISH_GP0 */
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PAD_CFG_NC(GPP_A18),
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/* A19 : ISH_GP1 ==> TRACKPAD_INT_L */
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PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST),
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/* A20 : ISH_GP2 ==> ISH_UART0_RXD */
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PAD_CFG_NC(GPP_A20),
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/* A21 : ISH_GP3 */
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PAD_CFG_NC(GPP_A21),
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/* A22 : ISH_GP4 */
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@ -186,10 +184,6 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF_1V8(GPP_D11, NONE, DEEP, NF1),
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/* D12 : ISH_SPI_MOSI ==> ISH_SPI_MOSI */
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PAD_CFG_NF_1V8(GPP_D12, NONE, DEEP, NF1),
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/* D13 : ISH_UART0_RXD ==> ISH_UART0_RXD */
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PAD_CFG_NF_1V8(GPP_D13, NONE, DEEP, NF1),
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/* D14 : ISH_UART0_TXD ==> ISH_UART0_TXD */
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PAD_CFG_NF_1V8(GPP_D14, NONE, DEEP, NF1),
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/* D15 : ISH_UART0_RTS# ==> NC */
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PAD_CFG_NC(GPP_D15),
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/* D16 : ISH_UART0_CTS# ==> NC */
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@ -388,3 +382,50 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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static const struct pad_config ish_enabled_gpio_table[] = {
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/* A19 : ISH_GP1 ==> TRACKPAD_INT_L
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* trackpad interrupt to ISH
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*/
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PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
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/* A20 : ISH_GP2 ==> ISH_UART0_RXD
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* ISH_UART0_RXD signal goes to this ISH GPIO pin.
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* It is used as wake up source in ISH firmware.
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* Implementation is in ISH firmware also.
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*/
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PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
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/* D13 : ISH_UART0_RXD ==> ISH_UART0_RXD */
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PAD_CFG_NF_1V8(GPP_D13, NONE, DEEP, NF1),
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/* D14 : ISH_UART0_TXD ==> ISH_UART0_TXD */
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PAD_CFG_NF_1V8(GPP_D14, NONE, DEEP, NF1),
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};
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static const struct pad_config ish_disabled_gpio_table[] = {
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/* A19 : GPP_A19 ==> TRACKPAD_INT_L
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* trackpad interrupt to PCH
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*/
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PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST),
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/* A20 : ISH_GP2 ==> NC */
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PAD_CFG_NC(GPP_A20),
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/* D13 : ISH_UART0_RXD ==> NC */
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PAD_CFG_NC(GPP_D13),
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/* D14 : ISH_UART0_TXD ==> NC */
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PAD_CFG_NC(GPP_D14),
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};
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const struct pad_config *variant_sku_gpio_table(size_t *num)
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{
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const struct pad_config *board_gpio_tables;
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const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH);
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if (dev && dev->enabled) {
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*num = ARRAY_SIZE(ish_enabled_gpio_table);
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board_gpio_tables = ish_enabled_gpio_table;
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} else {
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*num = ARRAY_SIZE(ish_disabled_gpio_table);
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board_gpio_tables = ish_disabled_gpio_table;
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}
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return board_gpio_tables;
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}
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