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mainboard/google/soraka: Configure GPP_B8 in bootblock 

GPP_B8 acts as input to the inverter whose output controls PERST#
signal to wifi module. Out of reset, GPP_B8 is configured as
input by default. Since there is no external pull-down on it, this
line is floating and results in PERST# being asserted until ramstage
where the GPIO was originally configured. Because of this the wifi
chip is not ready during the PCIe initialization step. Move the
configuration of GPP_B8 to bootblock so that wifi device is taken out
of reset as early as possible.

BUG=b:64181150,b:62726961
TEST=Verified with warm reboot and suspend-resume stress test that
wifi is still functional.

Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Furquan Shaikh 2017-08-02 19:06:05 -07:00 committed by Furquan Shaikh
parent 5a89b40b15
commit 0767f89be4
1 changed files with 3 additions and 2 deletions
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5
src/mainboard/google/poppy/variants/soraka/gpio.c
View File

@ -78,8 +78,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
/* B7 : SRCCLKREQ2# ==> NC */
PAD_CFG_NC(GPP_B7),
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
PAD_CFG_GPO(GPP_B8, 0, DEEP),
/* B9 : SRCCLKREQ4# ==> NC */
PAD_CFG_NC(GPP_B9),
/* B10 : SRCCLKREQ5# ==> NC */
@ -371,6 +369,9 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
PAD_CFG_GPO(GPP_B8, 0, DEEP),
#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),