mb/up/squared: Do RAM config based on SKU ID
TESTED=UP Squared Change-Id: Ic121652213d5b1f65cff2f3096e919a3cf88db72 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34838 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
Patrick Georgi
parent
d415c206b5
commit
07734c91d5
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@ -342,10 +342,10 @@ static const struct pad_config gpio_table[] = {
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_PAD_CFG_STRUCT(GPIO_213, 0x44000201, 0x00003000),
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// GPIO
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_PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x00000000),
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_PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x00003300),
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// GPIO
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_PAD_CFG_STRUCT(GPIO_215, 0x44000100, 0x00000000),
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_PAD_CFG_STRUCT(GPIO_215, 0x44000100, 0x00003300),
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// *THERMTRIP_N
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_PAD_CFG_STRUCT(PMIC_THERMTRIP_B, 0x44000400, 0x00003000),
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@ -15,11 +15,20 @@
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#include <string.h>
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#include <soc/romstage.h>
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#include <soc/gpio_apl.h>
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#include <fsp/api.h>
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#include <FspmUpd.h>
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#include <console/console.h>
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#include <gpio.h>
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#include "gpio.h"
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/*
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* Offsets:
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* - GPIO_214: 0xd8
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* - GPIO_215: 0xe0
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*/
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static const uint8_t memory_skuid_pads[] = { GPIO_214, GPIO_215 };
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static const uint8_t ch0_bit_swizzling[] = {
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0x0D, 0x0A, 0x08, 0x0B, 0x0C, 0x0F, 0x0E, 0x09,
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0x06, 0x00, 0x03, 0x04, 0x07, 0x01, 0x05, 0x02,
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@ -48,49 +57,103 @@ static const uint8_t ch3_bit_swizzling[] = {
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0x19, 0x1F, 0x1D, 0x1B, 0x1E, 0x18, 0x1C, 0x1A
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};
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/*
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* GPIO215 GPIO214 Memory size
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* 0 0 2 GiB
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* 0 1 4 GiB
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* 1 0 8 GiB
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* 1 1 Reserved
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*/
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static uint8_t get_memory_skuid(void)
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{
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uint8_t memory_skuid = 0;
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for (uint8_t i = 0; i < ARRAY_SIZE(memory_skuid_pads); i++) {
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uint8_t rx_state = gpio_get(memory_skuid_pads[i]);
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memory_skuid |= rx_state << i;
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}
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return memory_skuid;
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}
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void mainboard_memory_init_params(FSPM_UPD *memupd)
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{
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printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__);
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FSP_M_CONFIG *config = &memupd->FspmConfig;
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gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
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memupd->FspmConfig.Package = 0x1; // 0x0
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memupd->FspmConfig.Profile = 0xB; // 0x19
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memupd->FspmConfig.MemoryDown = 0x1; // 0x0
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memupd->FspmConfig.DDR3LPageSize = 0x0; // 0x1
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memupd->FspmConfig.DIMM0SPDAddress = 0x0; // 0xa0
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memupd->FspmConfig.DIMM1SPDAddress = 0x0; // 0xa4
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memupd->FspmConfig.RmtCheckRun = 0x3; // 0x0
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memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0
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memupd->FspmConfig.EnhancePort8xhDecoding = 0x0; // 0x1
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memupd->FspmConfig.NpkEn = 0x0; // 0x3
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memupd->FspmConfig.PrimaryVideoAdaptor = 0x2; // 0x0
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uint8_t memory_skuid = get_memory_skuid();
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printk(BIOS_DEBUG, "MAINBOARD: Found memory SKU ID: 0x%02x\n", memory_skuid);
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memupd->FspmConfig.Ch0_RankEnable = 0x1; // 0x0
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memupd->FspmConfig.Ch0_DeviceWidth = 0x1; // 0x0
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memupd->FspmConfig.Ch0_DramDensity = 0x2; // 0x0
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memupd->FspmConfig.Ch0_Option = 0x3; // 0x0
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memupd->FspmConfig.Ch1_RankEnable = 0x1; // 0x0
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memupd->FspmConfig.Ch1_DeviceWidth = 0x1; // 0x0
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memupd->FspmConfig.Ch1_DramDensity = 0x2; // 0x0
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memupd->FspmConfig.Ch1_Option = 0x3; // 0x0
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memupd->FspmConfig.Ch2_RankEnable = 0x1; // 0x0
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memupd->FspmConfig.Ch2_DeviceWidth = 0x1; // 0x0
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memupd->FspmConfig.Ch2_DramDensity = 0x2; // 0x0
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memupd->FspmConfig.Ch2_Option = 0x3; // 0x0
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memupd->FspmConfig.Ch3_RankEnable = 0x1; // 0x0
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memupd->FspmConfig.Ch3_DeviceWidth = 0x1; // 0x0
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memupd->FspmConfig.Ch3_DramDensity = 0x2; // 0x0
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memupd->FspmConfig.Ch3_Option = 0x3; // 0x0
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memupd->FspmConfig.StartTimerTickerOfPfetAssert = 0x4E20; // 0x0
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switch (memory_skuid) {
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case 0: /* 2GB */
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config->DualRankSupportEnable = 0;
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config->Ch0_RankEnable = 1;
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config->Ch0_DramDensity = 2;
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config->Ch1_RankEnable = 1;
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config->Ch1_DramDensity = 2;
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config->Ch2_RankEnable = 0;
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config->Ch3_RankEnable = 0;
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printk(BIOS_INFO, "MAINBOARD: Found supported memory: 2GB\n");
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break;
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case 1: /* 4GB */
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config->DualRankSupportEnable = 1;
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config->Ch0_RankEnable = 1;
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config->Ch0_DramDensity = 2;
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config->Ch1_RankEnable = 1;
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config->Ch1_DramDensity = 2;
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config->Ch2_RankEnable = 1;
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config->Ch2_DramDensity = 2;
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config->Ch3_RankEnable = 1;
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config->Ch3_DramDensity = 2;
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printk(BIOS_INFO, "MAINBOARD: Found supported memory: 4GB\n");
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break;
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case 2: /* 8GB */
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config->DualRankSupportEnable = 1;
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config->Ch0_RankEnable = 3;
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config->Ch0_DramDensity = 2;
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config->Ch1_RankEnable = 3;
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config->Ch1_DramDensity = 2;
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config->Ch2_RankEnable = 3;
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config->Ch2_DramDensity = 2;
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config->Ch3_RankEnable = 3;
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config->Ch3_DramDensity = 2;
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printk(BIOS_INFO, "MAINBOARD: Found supported memory: 8GB\n");
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break;
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default:
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printk(BIOS_INFO, "MAINBOARD: No supported memory found!\n");
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break;
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}
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memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &ch0_bit_swizzling,
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config->Package = 0x1; // 0x0
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config->Profile = 0xB; // 0x19
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config->MemoryDown = 0x1; // 0x0
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config->DDR3LPageSize = 0x0; // 0x1
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config->DIMM0SPDAddress = 0x0; // 0xa0
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config->DIMM1SPDAddress = 0x0; // 0xa4
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config->RmtCheckRun = 0x3; // 0x0
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config->RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0
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config->EnhancePort8xhDecoding = 0x0; // 0x1
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config->NpkEn = 0x0; // 0x3
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config->PrimaryVideoAdaptor = 0x2; // 0x0
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config->Ch0_DeviceWidth = 0x1; // 0x0
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config->Ch0_Option = 0x3; // 0x0
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config->Ch1_DeviceWidth = 0x1; // 0x0
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config->Ch1_Option = 0x3; // 0x0
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config->Ch2_DeviceWidth = 0x1; // 0x0
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config->Ch2_Option = 0x3; // 0x0
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config->Ch3_DeviceWidth = 0x1; // 0x0
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config->Ch3_Option = 0x3; // 0x0
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config->StartTimerTickerOfPfetAssert = 0x4E20; // 0x0
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memcpy(config->Ch0_Bit_swizzling, &ch0_bit_swizzling,
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sizeof(ch0_bit_swizzling));
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memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &ch1_bit_swizzling,
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memcpy(config->Ch1_Bit_swizzling, &ch1_bit_swizzling,
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sizeof(ch1_bit_swizzling));
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memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &ch2_bit_swizzling,
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memcpy(config->Ch2_Bit_swizzling, &ch2_bit_swizzling,
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sizeof(ch2_bit_swizzling));
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memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &ch3_bit_swizzling,
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memcpy(config->Ch3_Bit_swizzling, &ch3_bit_swizzling,
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sizeof(ch3_bit_swizzling));
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}
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