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nb/intel/ironlake: Add QPI Link register definitions 

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: Id226a2fdcbd0fe48822c4f65746e14fb00db6b2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-07-22 17:47:06 +02:00 committed by Patrick Georgi
parent 93d9517795
commit 0814357646
2 changed files with 10 additions and 5 deletions
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5
src/northbridge/intel/ironlake/ironlake.h
View File

@ -65,6 +65,11 @@
*/
#define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0)
#define QPI_QPILCP 0x40 /* QPI Link Capability */
#define QPI_QPILCL 0x48 /* QPI Link Control */
#define QPI_QPILS 0x50 /* QPI Link Status */
#define QPI_DEF_RMT_VN_CREDITS 0x58 /* Default Available Remote Credits */
/* Device 0:2.0 PCI configuration space (Graphics Device) */

10
src/northbridge/intel/ironlake/raminit.c
View File

@ -3950,11 +3950,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
MCHBAR8_OR(0x2ca8, 1); // guess
}
pci_read_config32(QPI_LINK_0, 0x048); // !!!!
pci_write_config32(QPI_LINK_0, 0x048, 0x140000);
pci_read_config32(QPI_LINK_0, 0x058); // !!!!
pci_write_config32(QPI_LINK_0, 0x058, 0x64555);
pci_read_config32(QPI_LINK_0, 0x058); // !!!!
pci_read_config32(QPI_LINK_0, QPI_QPILCL); // !!!!
pci_write_config32(QPI_LINK_0, QPI_QPILCL, 0x140000);
pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!!
pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555);
pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!!
pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!!
pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180);
gav(MCHBAR32(0x1af0)); // !!!!