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nb/intel/ironlake: Add definition for QPI Link PCI device 

On multi-socket platforms, there can be two QPI buses, each with its own
PCI device. We only have one QPI link on Arrandale, though. In case
support for multi-socket processors ever gets added, name it Link 0.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-07-22 17:30:49 +02:00 committed by Patrick Georgi
parent 67573371d5
commit 93d9517795
2 changed files with 10 additions and 5 deletions
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5
src/northbridge/intel/ironlake/ironlake.h
View File

@ -60,6 +60,11 @@
#define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */
#define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */
/*
* QPI Link 0
*/
#define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0)
/* Device 0:2.0 PCI configuration space (Graphics Device) */

10
src/northbridge/intel/ironlake/raminit.c
View File

@ -3950,11 +3950,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
MCHBAR8_OR(0x2ca8, 1); // guess
}
pci_read_config32(PCI_DEV(0xff, 2, 0), 0x048); // !!!!
pci_write_config32(PCI_DEV(0xff, 2, 0), 0x048, 0x140000);
pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!!
pci_write_config32(PCI_DEV(0xff, 2, 0), 0x058, 0x64555);
pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!!
pci_read_config32(QPI_LINK_0, 0x048); // !!!!
pci_write_config32(QPI_LINK_0, 0x048, 0x140000);
pci_read_config32(QPI_LINK_0, 0x058); // !!!!
pci_write_config32(QPI_LINK_0, 0x058, 0x64555);
pci_read_config32(QPI_LINK_0, 0x058); // !!!!
pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!!
pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180);
gav(MCHBAR32(0x1af0)); // !!!!