fixes for various wrong bits
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -30,7 +30,7 @@ static void hard_reset(void)
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set_bios_reset();
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/* enable cf9 */
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pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
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pci_write_config8(PCI_DEV(1, 0x04, 3), 0x41, 0xf1);
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/* reset */
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outb(0x0e, 0x0cf9);
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}
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@ -38,7 +38,7 @@ static void hard_reset(void)
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static void soft_reset(void)
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{
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
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pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
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}
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static void memreset_setup(void)
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@ -122,6 +122,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#include "mainboard/ibm/e325/resourcemap.c"
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@ -172,7 +173,7 @@ static void main(void)
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pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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setup_default_resource_map();
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setup_ibm_e325_resource_map();
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needs_reset = setup_coherent_ht_domain();
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
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if (needs_reset) {
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@ -103,7 +103,7 @@ CONF 0x3(0xffff0330):
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*
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*/
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static void setup_s2885_resource_map(void)
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static void setup_ibm_e325_resource_map(void)
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{
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static const unsigned int register_values[] = {
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/* Careful set limit registers before base registers which contain the enables */
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@ -355,7 +355,7 @@ static void setup_s2885_resource_map(void)
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* [31:24] Bus Number Limit i
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* This field defines the highest bus number in configuration regin i
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*/
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PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, ff000103,
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PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0xff000103,
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PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0,
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PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0,
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PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0,
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